23 #ifndef __CLRX_GPUID_H__ 24 #define __CLRX_GPUID_H__ 101 GPUARCH_MAX = GCN1_4_1
110 ARCH_SOUTHERN_ISLANDS = 1,
111 ARCH_SEA_ISLANDS = 2,
112 ARCH_VOLCANIC_ISLANDS = 4,
118 ARCH_GCN_1_0_1 = 0x3,
119 ARCH_GCN_1_1_2 = 0x6,
120 ARCH_GCN_1_1_2_4 = 0x1e,
121 ARCH_GCN_1_2_4 = 0x1c,
123 ARCH_GCN_ALL = 0xffff
149 REGCOUNT_NO_FLAT = 2,
150 REGCOUNT_NO_XNACK = 4,
151 REGCOUNT_NO_EXTRA = 0xffff
167 GPUSETUP_TGSIZE_EN = 1,
168 GPUSETUP_SCRATCH_EN = 2
212 cxuint priority,
cxuint floatMode,
bool privMode,
bool dx10clamp,
213 bool debugMode,
bool ieeeMode);
217 bool trapPresent,
cxuint dimMask,
cxuint defDimValues,
bool tgSizeEn,
uint32_t Flags
type for declaring various flags
Definition: Utilities.h:100
first iteration (Radeon HD7000 series)
virtual ~GPUIdException() noexcept=default
destructor
structure helper for AMDGPU architecture version
Definition: GPUId.h:203
GPUArchitecture getGPUArchitectureFromDeviceType(GPUDeviceType deviceType)
get GPUArchitecture from GPU device type
uint16_t GPUArchMask
GPU architecture mask (one bit represents single GPU architecture)
Definition: GPUId.h:105
GPUArchitecture getGPUArchitectureFromName(const char *name)
get GPU architecture from name
cxuint getDefaultDimMask(GPUArchitecture architecture, uint32_t pgmRSRC2)
get default dimMask from PGMRSRC2
cxuint getGPUMaxRegsNumByArchMask(GPUArchMask archMask, cxuint regType)
get maximum available registers for GPU (type: 0 - scalar, 1 - vector)
GPUArchitecture
GPU architecture.
Definition: GPUId.h:94
GPUId exception class.
Definition: GPUId.h:35
GPUDeviceType getLowestGPUDeviceTypeFromArchitecture(GPUArchitecture arch)
get lowest GPU device for architecture
GFX9 architecture with NN extensions (AMD VEGA 20)
GPUArchVersionTable
ADMGPUArchValues table type.
Definition: GPUId.h:222
bool isSpecialSGPRRegister(GPUArchMask archMask, cxuint index)
get maximum number of scalar register + extra scalar reg (VCC, FLAT_SCRATCH, ...) ...
void getGPUSetupMinRegistersNum(GPUArchitecture architecture, cxuint dimMask, cxuint userDataNum, Flags flags, cxuint *gprsOut)
get minimal number of required registers
bool isThisGPUArchitecture(GPUArchitecture requiredArch, GPUArchitecture thisArch)
check whether is this GPU architecture
uint32_t calculatePgmRSrc2(GPUArchitecture arch, bool scratchEn, cxuint userDataNum, bool trapPresent, cxuint dimMask, cxuint defDimValues, bool tgSizeEn, cxuint ldsSize, cxuint exceptions)
calculate PGMRSRC2 register value
const char * getGPUDeviceTypeName(GPUDeviceType deviceType)
get GPU device type name
size_t getGPUMaxLocalSize(GPUArchitecture architecture)
get maximum local size for GPU architecture
cxuint getGPUMaxRegistersNum(GPUArchitecture architecture, cxuint regType, Flags flags=0)
get maximum available registers for GPU (type: 0 - scalar, 1 - vector)
uint32_t major
arch major number
Definition: GPUId.h:205
uint32_t stepping
arch stepping number
Definition: GPUId.h:207
unsigned char cxbyte
unsigned byte
Definition: Config.h:229
uint32_t calculatePgmRSrc1(GPUArchitecture arch, cxuint vgprsNum, cxuint sgprsNum, cxuint priority, cxuint floatMode, bool privMode, bool dx10clamp, bool debugMode, bool ieeeMode)
calculate PGMRSRC1 register value
main namespace
Definition: AsmDefs.h:38
GFX9 architecture (AMD RX VEGA)
unsigned int cxuint
unsigned int
Definition: Config.h:237
size_t getGPUMaxGDSSize(GPUArchitecture architecture)
get maximum GDS size for GPU architecture
uint32_t minor
arch minor number
Definition: GPUId.h:206
GPUDeviceType
type of GPU device
Definition: GPUId.h:51
third iteration (Radeon Rx 300 series and Tonga)
ROCm (RadeonOpenCompute) format.
GPUIdException()=default
empty constructor
utilities for other libraries and programs
const char * getGPUArchitectureName(GPUArchitecture architecture)
get GPU architecture name
std::string message
message
Definition: Utilities.h:64
GPUDeviceType getGPUDeviceTypeFromName(const char *name)
get GPU device type from name
exception class
Definition: Utilities.h:61
AMDGPUArchVersion getGPUArchVersion(GPUDeviceType deviceType, GPUArchVersionTable table)
get AMD GPU architecture version for specific device type and driver
cxuint getGPUExtraRegsNum(GPUArchitecture architecture, cxuint regType, Flags flags)
get extra registers (like VCC,FLAT_SCRATCH)
second iteration (Radeon Rx 200 series)