source: CLRX/CLRadeonExtender/trunk/doc/GcnOperands.md @ 3469

Last change on this file since 3469 was 3469, checked in by matszpk, 10 months ago

CLRadeonExtender: CLRXDocs: Add first GCN 1.4 (GFX900) instructions.

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1### Operand encoding
2
3The GCN1.0/1.1 delivers maximum 104 registers (with VCC). Basic list of destination
4scalar operands have 128 entries. Source operands codes is in range 0-255.
5
6**Important**: Two SGPR's must be aligned to 2. Four or more SGPR's must be aligned to 4.
7This rule do not apply to vector instruction where is more complex rule:
8SGPR's can be unaligned only if SGPR register range do not cross line (4 SGPR registers).
9
10Following list describes all operand codes values:
11
12Code     | Name              | Description
13---------|-------------------|------------------------
140-103    | S0 - S103         | SGPR's (GCN1.0/1.1)
150-101    | S0 - S101         | SGPR's (GCN1.2)
16104-105  | FLAT_SCRATCH      | FLAT_SCRATCH register (GCN1.1)
17104      | FLAT_SCRATCH_LO   | Low half of FLAT_SCRATCH register (GCN1.1)
18105      | FLAT_SCRATCH_HI   | High half of FLAT_SCRATCH register (GCN1.1)
19102-103  | FLAT_SCRATCH      | FLAT_SCRATCH register (GCN1.2)
20102      | FLAT_SCRATCH_LO   | Low half of FLAT_SCRATCH register (GCN1.2)
21103      | FLAT_SCRATCH_HI   | High half of FLAT_SCRATCH register (GCN1.2)
22104-105  | XNACK_MASK        | XNACK_MASK register
23104      | XNACK_MASK_LO     | Low half of XNACK_MASK register
24105      | XNACK_MASK_HI     | High half of XNACK_MASK register
25106-107  | VCC               | VCC (vector carry register) two last SGPR's
26106      | VCC_LO            | Low half of VCC
27107      | VCC_HI            | High half of VCC
28108-109  | TBA               | Trap handler base address
29108      | TBA_LO            | Low half of TBA register
30109      | TBA_HI            | High half of TBA register
31110-111  | TMA               | Pointer to data in memory used by trap handler
32110      | TMA_LO            | Low half of TMA register
33111      | TMA_HI            | High half of TMA register
34112-123  | TTMP0 - TTMP11    | Trap handler temporary registers (GCN 1.0/1.1/1.2)
35108-123  | TTMP0 - TTMP15    | Trap handler temporary registers (GCN 1.4)
36124      | M0                | M0. Memory register
37125      | -                 | reserved
38126-127  | EXEC              | EXEC register
39126      | EXEC_LO           | Low half of EXEC register
40127      | EXEC_HI           | High half of EXEC register
41128      | 0                 | 0
42129-192  | 1-64              | 1 to 64 constant value
43193-208  | -1 - -16          | -1 to -16 constant value
44209-239  | -                 | reserved
45235      | SRC_SHARED_BASE   | Memory aperture
46236      | SRC_SHARED_LIMIT  | Memory aperture
47237      | SRC_PRIVATE_BASE  | Memory aperture
48238      | SRC_PRIVATE_LIMIT | Memory aperture
49239      | POPS_EXITING_WAVE_ID | Primitive Ordered Pixel Shading wave ID
50240      | 0.5               | 0.5 floating point value
51241      | -0.5              | -0.5 floating point value
52242      | 1.0               | 1.0 floating point value
53243      | -1.0              | -1.0 floating point value
54244      | 2.0               | 2.0 floating point value
55245      | -2.0              | -2.0 floating point value
56246      | 4.0               | 4.0 floating point value
57247      | -4.0              | -4.0 floating point value
58248      | 1/(2*PI)          | 1/(2*PI)
59249      | --                | SDWA dword (GCN1.2)
60250      | --                | DPP dword (GCN1.2)
61251      | VCCZ              | VCCZ register
62252      | EXECZ             | EXECZ register
63253      | SCC               | SCC register
64254      | LDS_DIRECT        | LDS direct access
65254      | LDS               | LDS direct access
66254      | SRC_LDS_DIRECT    | LDS direct access
67255      | 255               | Literal constant (follows instruction dword)
68256-511  | V0-V255           | VGPR's (only VOP3 encoding operands)
69
70### Operand syntax
71
72Single operands can be given by their name: `s0`, `v54`. CLRX assemblers accepts syntax with
73brackets: `s[0]`, `s[z]`, `v[66]`. In many instructions operands are
7464-bit, 96-bit or even 128-bit. These operands consists several registers that can be
75expressed by ranges: `v[3:4]`, `s[8:11]`, `s[16:23]`, where second value is
76last register's number.
77
78Names of the registers are case-insensitive.
79
80Constant values are automatically resolved if expression have already value.
81The 1/(2*PI), 1.0, -2.0 and other floating point constant values will be
82resolved if that accurate floating point value will be given.
83
84In instruction syntax, operands are listed by name of the encoding field. Optionally, in
85parentheses is given number of the registers. The ranges of number of a registers are in
86form 'START:LAST'. Example:
87
88Syntax: S_SUB_I32 SDST, SSRC0, SSRC1 
89Syntax: S_AND_B64 SDST(2), SSRC0(2), SSRC1(2) 
90Syntax: S_AND_B64 SDST(2), SSRC0(2), SSRC1(2:4) 
91
92### Constants and literals
93
94There are two ways to supply immediate value to GCN instruction: first is builtin constants
95(both  integer and floating points) and second is 32-bit immediate. Some type encoding
96allow to supply immediate with various size (16-bit or 12-bit).
97
98The literals are differently treated for scalar/vector instructions and for
99double floating point operands in vector instructions.
100In scalar or vector instructions if operand is 64-bit, the literal value is exact value
10164-bit value (sign or zero extended). By contrast, in FP64 operands in vector instructions,
102for 64-bit operand, the literal is higher 32-bits of value (lower 32-bit are zero). Unhapilly, the CLRX assembler always encodes and decodes literal immediate as 32-bit
103value (except floating values).
104The immediate constants are always exact value, either for 32-bit and 64-bit operands.
105For example, instructions `v_frexp_exp_i32_f64 v3, lit(45)` and
106`v_frexp_exp_i32_f64 v3, 45` generates different results, because literal and constant
107will be have different meaning.
108
109**NOTE:** These same literals and constants gives different values for 64-bit operand in
110vector instructions. To distinguish values, please use `lit()` function.
111
112**OLD_VERSIONS**: This version of CLRadeonExtender adds '--buggyFPLit' option to support
113sources for older versions (to 0.1.2). Versions to 0.1.2 incorrectly handles floating
114point literals and constants due to wrong assumptions. This and later versions fix
115that behaviour.
116
117Old and buggy behaviour:
118
119* support only half and single floating point literals (and constants)
120* shorten literals to constant only for single floating point literals
121
122New behaviour:
123
124* support half, single and double (only higher 32-bits) floating point literals
125(and constants)
126* shorten literals to constant for half, single and double literals (type depends
127from operand type)
128
129### Hardware registers
130
131These register could be read or written by S_GETREG_\* and S_SETREG_\* instruction.
132
133List of hardware registers:
134
135* GPR_ALLOC, HWREG_GPR_ALLOC -
136* HW_ID, HWREG_HW_ID -
137* IB_DBG0, HWREG_DBG0 -
138* IB_STS, HWREG_IB_STS -
139* INST_DW0, HWREG_INST_DW0 -
140* INST_DW1, HWREG_INST_DW1 -
141* LDS_ALLOC, HWREG_LDS_ALLOC -
142* MODE, HWREG_MODE -
143* PC_HI, HWREG_PC_HI -
144* PC_LO, HWREG_PC_LO -
145* STATUS, HWREG_STATUS -
146* TRAPSTS, HWREG_TRAPSTS -
147
148### LDS direct access
149
150The LDS direct access allow to access LDS memory from VOP instruction directly by supplying
151LDS, LDS_DIRECT or SRC_LDS_DIRECT keyword on the first source operand. Then data from
152LDS will be used on place that operand.
153
154The M0 must hold the offset in bytes (in 0-15 bits) and format of the data (in bits 16-18).
155Table of formats:
156
157 Value | Format
158-------|----------------
1590      | Unsigned byte
1601      | Unsigned 16-bit word
1612      | Unsigned 32-bit word
1623      | unused (same as 2)
1634      | Signed byte
1645      | Signed 16-bit word
165
166A LDS direct access doesn't require `S_WAITCNT LGKMCNT(0)` (??? check).
167
168### Parametrizable modifiers
169
170Many an instruction's modifiers can have parameter that have value 0 or 1. This feature
171allow to easily parametrize modifiers. The non-zero (to 0.1.5 version 1 value)
172value enables modifier, zero disables it. `tfe:0` disable TFE modifier, `tfe:1` enables it.
173The value of parameter is an expression.
174The `omod` modifier with parameter (expression) replaces `mul` and `div` modifiers.
175The `format` in MTBUF encoding is also parametrizable if data and/or
176number format expression will be preceded by `@` character (example: `format[@1,@4]`).
177Special case is `bound_ctrl`. To parametrize bound_ctrl you must use syntax:
178`bound_ctrl:0:expr` or `bound_ctrl:1:expr`.
179The `abs`, `neg` and `sext` modifiers with parameter (expression) allow to set what
180source operand will have operand modifier. Number of bit of value refer to number of source operand. The `abs`, `neg` and `sext` modifiers accepts binary array of expressions like
181`[bit0,bit1,...]`.
182
183The HW registers and send message parameters (message and GSOP) is parametrizable if
184they will be preceded by `@` (example: `hwreg(@5, 8, 16)`).
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