Changeset 3067 in CLRX
- Timestamp:
- May 15, 2017, 6:17:43 PM (2 years ago)
- Location:
- CLRadeonExtender/trunk
- Files:
-
- 4 edited
-
amdasm/GCNDisasm.cpp (modified) (3 diffs)
-
amdasm/GCNInstructions.cpp (modified) (4 diffs)
-
amdasm/GCNInternals.h (modified) (1 diff)
-
tests/amdasm/GCNDisasmOpc14.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
CLRadeonExtender/trunk/amdasm/GCNDisasm.cpp
r3064 r3067 1799 1799 char* bufPtr = bufStart; 1800 1800 const bool isGCN12 = ((arch&ARCH_GCN_1_2_4)!=0); 1801 const bool isGCN14 = ((arch&ARCH_RXVEGA)!=0); 1801 1802 const cxuint opcode = (isGCN12) ? ((insnCode>>16)&0x3ff) : ((insnCode>>17)&0x1ff); 1802 1803 … … 1939 1940 addSpaces(bufPtr, spacesToAdd-1); 1940 1941 1942 if (isGCN14 && (gcnInsn.mode & GCN_VOP3_OPSEL) != 0 && (insnCode & 0x7800) != 0) 1943 { // insnCode 1944 putChars(bufPtr, " op_sel:[", 9); 1945 *bufPtr++ = (insnCode&0x800) ? '1' : '0'; 1946 *bufPtr++ = ','; 1947 *bufPtr++ = (insnCode&0x1000) ? '1' : '0'; 1948 if (vsrc1Used) 1949 { 1950 *bufPtr++ = ','; 1951 *bufPtr++ = (insnCode&0x2000) ? '1' : '0'; 1952 } 1953 if (vsrc2Used) 1954 { 1955 *bufPtr++ = ','; 1956 *bufPtr++ = (insnCode&0x4000) ? '1' : '0'; 1957 } 1958 *bufPtr++ = ']'; 1959 } 1960 1941 1961 const cxuint omod = (insnCode2>>27)&3; 1942 1962 if (omod != 0) … … 1993 2013 if ((insnCode2 & (1U<<31)) != 0) 1994 2014 putChars(bufPtr, " neg2", 5); 2015 } 2016 2017 if (isGCN14 && (gcnInsn.mode & GCN_VOP3_OPSEL) == 0 && (insnCode & 0x7800) != 0 && 2018 gcnInsn.encoding != GCNENC_VOP3B) 2019 { 2020 putChars(bufPtr, " op_sel=", 8); 2021 bufPtr += itocstrCStyle((insnCode>>11)&15, bufPtr, 6, 16); 1995 2022 } 1996 2023 -
CLRadeonExtender/trunk/amdasm/GCNInstructions.cpp
r3066 r3067 1881 1881 { "v_fma_f64", GCNENC_VOP3A, GCN_REG_ALL_64, 460, ARCH_GCN_1_2_4 }, 1882 1882 { "v_lerp_u8", GCNENC_VOP3A, GCN_STDMODE, 461, ARCH_GCN_1_2_4 }, 1883 { "v_alignbit_b32", GCNENC_VOP3A, GCN_ STDMODE,462, ARCH_GCN_1_2_4 },1884 { "v_alignbyte_b32", GCNENC_VOP3A, GCN_ STDMODE,463, ARCH_GCN_1_2_4 },1883 { "v_alignbit_b32", GCNENC_VOP3A, GCN_VOP3_OPSEL, 462, ARCH_GCN_1_2_4 }, 1884 { "v_alignbyte_b32", GCNENC_VOP3A, GCN_VOP3_OPSEL, 463, ARCH_GCN_1_2_4 }, 1885 1885 { "v_min3_f32", GCNENC_VOP3A, GCN_STDMODE, 464, ARCH_GCN_1_2_4 }, 1886 1886 { "v_min3_i32", GCNENC_VOP3A, GCN_STDMODE, 465, ARCH_GCN_1_2_4 }, … … 1913 1913 { "v_fma_f16", GCNENC_VOP3A, GCN_STDMODE, 494, ARCH_RX3X0 }, 1914 1914 { "v_div_fixup_f16", GCNENC_VOP3A, GCN_STDMODE, 495, ARCH_RX3X0 }, 1915 { "v_mad_legacy_f16", GCNENC_VOP3A, GCN_ STDMODE,490, ARCH_RXVEGA },1916 { "v_mad_legacy_u16", GCNENC_VOP3A, GCN_ STDMODE,491, ARCH_RXVEGA },1917 { "v_mad_legacy_i16", GCNENC_VOP3A, GCN_ STDMODE,492, ARCH_RXVEGA },1918 { "v_fma_legacy_f16", GCNENC_VOP3A, GCN_ STDMODE,494, ARCH_RXVEGA },1919 { "v_div_fixup_legacy_f16", GCNENC_VOP3A, GCN_ STDMODE,495, ARCH_RXVEGA },1915 { "v_mad_legacy_f16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 490, ARCH_RXVEGA }, 1916 { "v_mad_legacy_u16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 491, ARCH_RXVEGA }, 1917 { "v_mad_legacy_i16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 492, ARCH_RXVEGA }, 1918 { "v_fma_legacy_f16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 494, ARCH_RXVEGA }, 1919 { "v_div_fixup_legacy_f16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 495, ARCH_RXVEGA }, 1920 1920 { "v_cvt_pkaccum_u8_f32",GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 496, ARCH_GCN_1_2_4 }, 1921 { "v_mad_u32_u16", GCNENC_VOP3A, GCN_ STDMODE,497, ARCH_RXVEGA },1922 { "v_mad_i32_i16", GCNENC_VOP3A, GCN_ STDMODE,498, ARCH_RXVEGA },1921 { "v_mad_u32_u16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 497, ARCH_RXVEGA }, 1922 { "v_mad_i32_i16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 498, ARCH_RXVEGA }, 1923 1923 { "v_xad_u32", GCNENC_VOP3A, GCN_STDMODE, 499, ARCH_RXVEGA }, 1924 { "v_min3_f16", GCNENC_VOP3A, GCN_ STDMODE,500, ARCH_RXVEGA },1925 { "v_min3_i16", GCNENC_VOP3A, GCN_ STDMODE,501, ARCH_RXVEGA },1926 { "v_min3_u16", GCNENC_VOP3A, GCN_ STDMODE,502, ARCH_RXVEGA },1927 { "v_max3_f16", GCNENC_VOP3A, GCN_ STDMODE,503, ARCH_RXVEGA },1928 { "v_max3_i16", GCNENC_VOP3A, GCN_ STDMODE,504, ARCH_RXVEGA },1929 { "v_max3_u16", GCNENC_VOP3A, GCN_ STDMODE,505, ARCH_RXVEGA },1930 { "v_med3_f16", GCNENC_VOP3A, GCN_ STDMODE,506, ARCH_RXVEGA },1931 { "v_med3_i16", GCNENC_VOP3A, GCN_ STDMODE,507, ARCH_RXVEGA },1932 { "v_med3_u16", GCNENC_VOP3A, GCN_ STDMODE,508, ARCH_RXVEGA },1924 { "v_min3_f16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 500, ARCH_RXVEGA }, 1925 { "v_min3_i16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 501, ARCH_RXVEGA }, 1926 { "v_min3_u16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 502, ARCH_RXVEGA }, 1927 { "v_max3_f16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 503, ARCH_RXVEGA }, 1928 { "v_max3_i16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 504, ARCH_RXVEGA }, 1929 { "v_max3_u16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 505, ARCH_RXVEGA }, 1930 { "v_med3_f16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 506, ARCH_RXVEGA }, 1931 { "v_med3_i16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 507, ARCH_RXVEGA }, 1932 { "v_med3_u16", GCNENC_VOP3A, GCN_VOP3_OPSEL, 508, ARCH_RXVEGA }, 1933 1933 { "v_lshl_add_u32", GCNENC_VOP3A, GCN_STDMODE, 509, ARCH_RXVEGA }, 1934 1934 { "v_add_lshl_u32", GCNENC_VOP3A, GCN_STDMODE, 510, ARCH_RXVEGA }, … … 1948 1948 { "v_interp_p1lv_f16", GCNENC_VOP3A, GCN_VOP3_VINTRP_NEW|GCN_VINTRP_SRC2, 629, ARCH_GCN_1_2_4 }, 1949 1949 { "v_interp_p2_f16", GCNENC_VOP3A, GCN_VOP3_VINTRP_NEW|GCN_VINTRP_SRC2, 630, ARCH_RX3X0 }, 1950 { "v_interp_p2_legacy_f16", GCNENC_VOP3A, GCN_VOP3_VINTRP_NEW|GCN_VINTRP_SRC2, 630, ARCH_RXVEGA }, 1950 { "v_interp_p2_legacy_f16", GCNENC_VOP3A, 1951 GCN_VOP3_VINTRP_NEW|GCN_VINTRP_SRC2|GCN_VOP3_OPSEL, 630, ARCH_RXVEGA }, 1951 1952 { "v_interp_p2_f16", GCNENC_VOP3A, GCN_VOP3_VINTRP_NEW|GCN_VINTRP_SRC2, 631, ARCH_RXVEGA }, 1952 1953 { "v_add_f64", GCNENC_VOP3A, GCN_REG_ALL_64|GCN_SRC2_NONE,640, ARCH_GCN_1_2_4 }, … … 1975 1976 { "v_cvt_pk_u16_u32", GCNENC_VOP3A, GCN_SRC2_NONE, 663, ARCH_GCN_1_2_4 }, 1976 1977 { "v_cvt_pk_i16_i32", GCNENC_VOP3A, GCN_SRC2_NONE, 664, ARCH_GCN_1_2_4 }, 1977 { "v_cvt_pknorm_i16_f16", GCNENC_VOP3A, GCN_SRC2_NONE ,665, ARCH_RXVEGA },1978 { "v_cvt_pknorm_u16_f16", GCNENC_VOP3A, GCN_SRC2_NONE ,666, ARCH_RXVEGA },1978 { "v_cvt_pknorm_i16_f16", GCNENC_VOP3A, GCN_SRC2_NONE|GCN_VOP3_OPSEL, 665, ARCH_RXVEGA }, 1979 { "v_cvt_pknorm_u16_f16", GCNENC_VOP3A, GCN_SRC2_NONE|GCN_VOP3_OPSEL, 666, ARCH_RXVEGA }, 1979 1980 { "v_readlane_regrd_b32", GCNENC_VOP3A, GCN_SRC2_NONE|GCN_VOP3_DS1_SGPR, 667, ARCH_RXVEGA }, 1980 1981 { "v_add_i32", GCNENC_VOP3A, GCN_SRC2_NONE, 668, ARCH_RXVEGA }, 1981 1982 { "v_sub_i32", GCNENC_VOP3A, GCN_SRC2_NONE, 669, ARCH_RXVEGA }, 1982 { "v_add_i16", GCNENC_VOP3A, GCN_SRC2_NONE ,670, ARCH_RXVEGA },1983 { "v_sub_i16", GCNENC_VOP3A, GCN_SRC2_NONE ,671, ARCH_RXVEGA },1984 { "v_pack_b32_f16", GCNENC_VOP3A, GCN_SRC2_NONE ,672, ARCH_RXVEGA },1983 { "v_add_i16", GCNENC_VOP3A, GCN_SRC2_NONE|GCN_VOP3_OPSEL, 670, ARCH_RXVEGA }, 1984 { "v_sub_i16", GCNENC_VOP3A, GCN_SRC2_NONE|GCN_VOP3_OPSEL, 671, ARCH_RXVEGA }, 1985 { "v_pack_b32_f16", GCNENC_VOP3A, GCN_SRC2_NONE|GCN_VOP3_OPSEL, 672, ARCH_RXVEGA }, 1985 1986 { "v_mad_u64_u32", GCNENC_VOP3B, GCN_REG_DS2_64|GCN_DST_VCC_VSRC2, 488, ARCH_GCN_1_2_4 }, 1986 1987 { "v_mad_i64_i32", GCNENC_VOP3B, GCN_REG_DS2_64|GCN_DST_VCC_VSRC2, 489, ARCH_GCN_1_2_4 }, -
CLRadeonExtender/trunk/amdasm/GCNInternals.h
r3063 r3067 124 124 GCN_VOP3_MASK2 = 0x300, // mask for VOPx in VOP2 encodings 125 125 GCN_VINTRP_SRC2 = 0x1000, /// VOP3/VINTRP with source2 (third source) 126 GCN_VOP3_MASK3 = 0xf000, /// mask for VINTRP in VOP2 encodings 126 GCN_VOP3_MASK3 = 0x3000, /// mask for VINTRP in VOP2 encodings 127 GCN_VOP3_OPSEL = 0x4000, /// if instruction uses op_sel modifier 127 128 // DS encoding modes 128 129 GCN_ADDR_STD = 0x0, /// standard place of address -
CLRadeonExtender/trunk/tests/amdasm/GCNDisasmOpc14.cpp
r3066 r3067 282 282 { 0xd29f0037U, 0x0002b51bU, true, " v_sub_i16 v55, v27, v90\n" }, 283 283 { 0xd2a00037U, 0x0002b51bU, true, " v_pack_b32_f16 v55, v27, v90\n" }, 284 /* VOP3 - op_sel */ 285 { 0xd276082aU, 0x007402a7, true, 286 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[1,0,0,0]\n" }, 287 { 0xd276102aU, 0x007402a7, true, 288 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[0,1,0,0]\n" }, 289 { 0xd276182aU, 0x007402a7, true, 290 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[1,1,0,0]\n" }, 291 { 0xd276202aU, 0x007402a7, true, 292 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[0,0,1,0]\n" }, 293 { 0xd276282aU, 0x007402a7, true, 294 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[1,0,1,0]\n" }, 295 { 0xd276302aU, 0x007402a7, true, 296 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[0,1,1,0]\n" }, 297 { 0xd276382aU, 0x007402a7, true, 298 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[1,1,1,0]\n" }, 299 { 0xd276402aU, 0x007402a7, true, 300 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[0,0,0,1]\n" }, 301 { 0xd276482aU, 0x007402a7, true, 302 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[1,0,0,1]\n" }, 303 { 0xd276502aU, 0x007402a7, true, 304 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[0,1,0,1]\n" }, 305 { 0xd276582aU, 0x007402a7, true, 306 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[1,1,0,1]\n" }, 307 { 0xd276602aU, 0x007402a7, true, 308 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[0,0,1,1]\n" }, 309 { 0xd276682aU, 0x007402a7, true, 310 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[1,0,1,1]\n" }, 311 { 0xd276702aU, 0x007402a7, true, 312 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[0,1,1,1]\n" }, 313 { 0xd276782aU, 0x007402a7, true, 314 " v_interp_p2_legacy_f16 v42, s1, attr39.z, s29 op_sel:[1,1,1,1]\n" }, 315 /* VOP3 - op_sel in instructions */ 316 { 0xd1ce5837U, 0x07974d4fU, true, 317 " v_alignbit_b32 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 318 { 0xd1cf5837U, 0x07974d4fU, true, 319 " v_alignbyte_b32 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 320 { 0xd1ea5837U, 0x07974d4fU, true, 321 " v_mad_legacy_f16 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 322 { 0xd1eb5837U, 0x07974d4fU, true, 323 " v_mad_legacy_u16 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 324 { 0xd1ec5837U, 0x07974d4fU, true, 325 " v_mad_legacy_i16 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 326 { 0xd1ee5837U, 0x07974d4fU, true, 327 " v_fma_legacy_f16 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 328 { 0xd1ef5837U, 0x07974d4fU, true, 329 " v_div_fixup_legacy_f16 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 330 { 0xd1f45837U, 0x07974d4fU, true, 331 " v_min3_f16 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 332 { 0xd1f55837U, 0x07974d4fU, true, 333 " v_min3_i16 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 334 { 0xd1f65837U, 0x07974d4fU, true, 335 " v_min3_u16 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 336 { 0xd1f75837U, 0x07974d4fU, true, 337 " v_max3_f16 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 338 { 0xd1f85837U, 0x07974d4fU, true, 339 " v_max3_i16 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 340 { 0xd1f95837U, 0x07974d4fU, true, 341 " v_max3_u16 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 342 { 0xd1fa5837U, 0x07974d4fU, true, 343 " v_med3_f16 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 344 { 0xd1fb5837U, 0x07974d4fU, true, 345 " v_med3_i16 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 346 { 0xd1fc5837U, 0x07974d4fU, true, 347 " v_med3_u16 v55, v79, v166, v229 op_sel:[1,1,0,1]\n" }, 348 { 0xd2995837U, 0x0002b51bU, true, 349 " v_cvt_pknorm_i16_f16 v55, v27, v90 op_sel:[1,1,0]\n" }, 350 { 0xd29a5837U, 0x0002b51bU, true, 351 " v_cvt_pknorm_u16_f16 v55, v27, v90 op_sel:[1,1,0]\n" }, 352 { 0xd29e5837U, 0x0002b51bU, true, 353 " v_add_i16 v55, v27, v90 op_sel:[1,1,0]\n" }, 354 { 0xd29f5837U, 0x0002b51bU, true, 355 " v_sub_i16 v55, v27, v90 op_sel:[1,1,0]\n" }, 356 { 0xd2a05837U, 0x0002b51bU, true, 357 " v_pack_b32_f16 v55, v27, v90 op_sel:[1,1,0]\n" }, 358 // if op_sel is not accepted 359 { 0xd1db5837U, 0x07974d4fU, true, 360 " v_sad_u16 v55, v79, v166, v229 op_sel=0xb\n" }, 284 361 { 0, 0, false, nullptr } 285 362 };
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