Changeset 3118 in CLRX

Timestamp:

Jun 2, 2017, 2:46:26 PM (17 months ago)

Author:

matszpk

Message:

CLRadeonExtender: Fixed registering RegVarUsage? in VOPx SDWA. Correct detecting of useenqueue (GFX9). Correct setting setup1 field kernel setup for GFX9.
Add missing entry in amdGpuArchValuesTbl for GFX9.

Location:

CLRadeonExtender/trunk

Files:

• amdasm/DisasmAmdCL2.cpp (modified) (3 diffs)
• amdasm/GCNAssembler.cpp (modified) (3 diffs)
• amdbin/AmdCL2BinGen.cpp (modified) (3 diffs)

CLRadeonExtender/trunk/amdasm/DisasmAmdCL2.cpp

@@ -359 +359 @@
 static AmdCL2KernelConfig genKernelConfig(size_t metadataSize, const cxbyte* metadata,
         size_t setupSize, const cxbyte* setup, const std::vector<size_t> samplerOffsets,
-        const std::vector<AmdCL2RelaEntry>& textRelocs)
+        const std::vector<AmdCL2RelaEntry>& textRelocs, bool isGCN14)
 {
     AmdCL2KernelConfig config{};
@@ -394 +394 @@
     if (ksetup1==0x2f) // if generic pointer support
         config.useGeneric = true;
-    else
+    else if (!isGCN14)
         config.useEnqueue = (ksetup1&0x20)!=0;
+    else // for GFX9 - check number of all registers must be 6+
+        config.useEnqueue = (setupData->sgprsNum+6 == setupData->sgprsNumAll);
     
     // get samplers
@@ -852 +854 @@
         if (doDumpConfig)
         {
+            const bool isGCN14 = getGPUArchitectureFromDeviceType(
+                        amdCL2Input->deviceType) >= GPUArchitecture::GCN1_4;
             AmdCL2KernelConfig config;
             if (amdCL2Input->is64BitMode)
                 config = genKernelConfig<AmdCL2Types64>(kinput.metadataSize,
                         kinput.metadata, kinput.setupSize, kinput.setup, samplerOffsets,
-                        kinput.textRelocs);
+                        kinput.textRelocs, isGCN14);
             else
                 config = genKernelConfig<AmdCL2Types32>(kinput.metadataSize,
                         kinput.metadata, kinput.setupSize, kinput.setup, samplerOffsets,
-                        kinput.textRelocs);
+                        kinput.textRelocs, isGCN14);
             dumpAmdCL2KernelConfig(output, config);
         }

CLRadeonExtender/trunk/amdasm/GCNAssembler.cpp

@@ -1603 +1603 @@
                     gcnVOPEnc, src0Op, extraMods, instrPlace))
             return false;
-        gcnAsm->instrRVUs[2].regField = GCNFIELD_DPPSDWA_SRC0;
+        if (gcnAsm->instrRVUs[2].regField != ASMFIELD_NONE)
+            gcnAsm->instrRVUs[2].regField = GCNFIELD_DPPSDWA_SRC0;
         
         if (extraMods.needSDWA && isGCN14)
@@ -1817 +1818 @@
                     gcnVOPEnc, src0Op, extraMods, instrPlace))
             return false;
-        gcnAsm->instrRVUs[1].regField = GCNFIELD_DPPSDWA_SRC0;
+        if (gcnAsm->instrRVUs[1].regField != ASMFIELD_NONE)
+            gcnAsm->instrRVUs[1].regField = GCNFIELD_DPPSDWA_SRC0;
         if (extraMods.needSDWA && isGCN14)
         {   // fix for extra type operand from SDWA
             AsmRegVarUsage* rvus = gcnAsm->instrRVUs;
-            if (rvus[2].regField != ASMFIELD_NONE && src0Op.range.isNonVGPR())
-                rvus[2].regField = GCNFIELD_DPPSDWA_SSRC0;
+            if (rvus[1].regField != ASMFIELD_NONE && src0Op.range.isNonVGPR())
+                rvus[1].regField = GCNFIELD_DPPSDWA_SSRC0;
         }
     }
@@ -2010 +2012 @@
                     gcnVOPEnc, src0Op, extraMods, instrPlace))
             return false;
-        gcnAsm->instrRVUs[1].regField = GCNFIELD_DPPSDWA_SRC0;
+        if (gcnAsm->instrRVUs[1].regField != ASMFIELD_NONE)
+            gcnAsm->instrRVUs[1].regField = GCNFIELD_DPPSDWA_SRC0;
         
         if (extraMods.needSDWA && isGCN14)
         {   // fix for extra type operand from SDWA
             AsmRegVarUsage* rvus = gcnAsm->instrRVUs;
-            if (rvus[2].regField != ASMFIELD_NONE && src0Op.range.isNonVGPR())
-                rvus[2].regField = GCNFIELD_DPPSDWA_SSRC0;
-            if (rvus[3].regField != ASMFIELD_NONE)
-                rvus[3].regField = GCNFIELD_VOP_SSRC1;
+            if (rvus[1].regField != ASMFIELD_NONE && src0Op.range.isNonVGPR())
+                rvus[1].regField = GCNFIELD_DPPSDWA_SSRC0;
+            if (rvus[2].regField != ASMFIELD_NONE)
+                rvus[2].regField = GCNFIELD_VOP_SSRC1;
         }
     }

CLRadeonExtender/trunk/amdbin/AmdCL2BinGen.cpp

@@ -1153 +1153 @@
     fob.writeArray(40, kernelSetupBytesAfter8);
     IntAmdCL2SetupData setupData;
-    const cxuint neededExtraSGPRsNum = arch==GPUArchitecture::GCN1_2 ? 4 : 2;
+    const cxuint neededExtraSGPRsNum = arch>=GPUArchitecture::GCN1_2 ? 4 : 2;
     const cxuint extraSGPRsNum = (config.useEnqueue || config.useGeneric) ?
                 neededExtraSGPRsNum : 0;
@@ -1175 +1175 @@
     else if (config.useArgs)
         setup1 = 0x9;
+    if (arch==GPUArchitecture::GCN1_4)
+        setup1 |= 0x20;
     
     SLEV(setupData.pgmRSRC2, calculatePgmRSRC2(config, arch));
@@ -1835 +1837 @@
     { 8, 0, 4 }, // GPUDeviceType::ELLESMERE
     { 8, 0, 4 }, // GPUDeviceType::BAFFIN
-    { 8, 0, 4 }  // GPUDeviceType::GFX804
+    { 8, 0, 4 }, // GPUDeviceType::GFX804
+    { 9, 0, 0 }  // GPUDeviceType::GFX900
 };