Changeset 3894 in CLRX

Timestamp:

Mar 12, 2018, 5:10:13 PM (13 months ago)

Author:

matszpk

Message:

CLRadeonExtender: Renumber the testcases in the comments.

File:

• CLRadeonExtender/trunk/tests/amdasm/AsmRegAllocCase2.cpp (modified) (10 diffs)

CLRadeonExtender/trunk/tests/amdasm/AsmRegAllocCase2.cpp

@@ -27 +27 @@
 const AsmSSADataCase ssaDataTestCases2Tbl[] =
 {
-    {   // 27 - conflicts inside routines
+    {   // 0 - conflicts inside routines
         R"ffDXD(.regvar sa:s:8, va:v:8
         s_mov_b32 sa[2], s4
@@ -189 +189 @@
         true, ""
     },
-    {  // 28 - res second point cache test 1
+    {  // 1 - res second point cache test 1
         R"ffDXD(.regvar sa:s:8, va:v:8, xa:s:8
         s_mov_b32 sa[2], s4
@@ -384 +384 @@
         true, ""
     },
-    {   // 29 - cache test 2: loop
+    {   // 2 - cache test 2: loop
         R"ffDXD(.regvar sa:s:8, va:v:8, xa:s:8
         s_mov_b32 sa[2], s4
@@ -529 +529 @@
     },
 #if 0
-    {   // 30 - routine with loop
+    {   // 3 - routine with loop
         R"ffDXD(.regvar sa:s:8, va:v:8, xa:s:8
         s_mov_b32 sa[2], s4
@@ -665 +665 @@
     }
 #endif
-    {   // 31 - routine with condition
+    {   // 4 - routine with condition
         R"ffDXD(.regvar sa:s:8, va:v:8, xa:s:8
         s_mov_b32 sa[2], s4
@@ -789 +789 @@
         true, ""
     },
-    {   // 32 - two routines with common code
+    {   // 5 - two routines with common code
         R"ffDXD(.regvar sa:s:8, va:v:8, xa:s:8
         s_mov_b32 sa[2], s4
@@ -936 +936 @@
         true, ""
     },
-    {   // 33 - simple call, more complex routine (reduce with reads)
+    {   // 6 - simple call, more complex routine (reduce with reads)
         R"ffDXD(.regvar sa:s:8, va:v:8
         s_mov_b32 sa[2], s4
@@ -1037 +1037 @@
         true, ""
     },
-    {   // 34 - retssa tests
+    {   // 7 - retssa tests
         R"ffDXD(.regvar sa:s:8, va:v:8
         s_mov_b32 sa[2], s4
@@ -1249 +1249 @@
         true, ""
     },
-    {   // 35 - retssa tests
+    {   // 8 - retssa tests
         R"ffDXD(.regvar sa:s:8, va:v:8
         s_mov_b32 sa[2], s4
@@ -1409 +1409 @@
         true, ""
     },
-    {   // 35 - retssa tests
+    {   // 9 - retssa tests
         R"ffDXD(.regvar sa:s:10, va:v:8
         s_mov_b32 sa[2], s4