Changes between Version 2 and Version 3 of GcnInstrsSop1


Ignore:
Timestamp:
11/15/15 21:00:20 (8 years ago)
Author:
trac
Comment:

--

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  • GcnInstrsSop1

    v2 v3  
    321321<h3>Instruction set</h3>
    322322<p>Alphabetically sorted instruction list:</p>
     323<h4>S_AND_SAVEEXEC_B64</h4>
     324<p>Opcode: 36 (0x24) for GCN 1.0/1.1; 32 (0x20) for GCN 1.2<br />
     325Syntax: S_AND_SAVEEXEC_B64 SDST(2), SDST(2)<br />
     326Description: Store EXEC register to SDST. Make bitwise AND on SSRC0 and EXEC
     327and store result to EXEC. If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
     328SDST and SSRC0 are 64-bit.<br />
     329Operation:<br />
     330<code>SDST = EXEC
     331EXEC = SSRC0 &amp; EXEC
     332SCC = EXEC!=0</code></p>
     333<h4>S_ANDN2_SAVEEXEC_B64</h4>
     334<p>Opcode: 39 (0x27) for GCN 1.0/1.1; 35 (0x23) for GCN 1.2<br />
     335Syntax: S_AND_SAVEEXEC_B64 SDST(2), SDST(2)<br />
     336Description: Store EXEC register to SDST. Make bitwise AND on SSRC0 and negated EXEC
     337and store result to EXEC. If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
     338SDST and SSRC0 are 64-bit.<br />
     339Operation:<br />
     340<code>SDST = EXEC
     341EXEC = SSRC0 &amp; EXEC
     342SCC = EXEC!=0</code></p>
    323343<h4>S_BCNT0_I32_B32</h4>
    324344<p>Opcode: 13 (0xd) for GCN 1.0/1.1; 10 (0xa) for GCN 1.2<br />
    … …  
    326346Description: Count zero bits in SSRC0 and store result to SDST.
    327347If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.<br />
     348Operation:<br />
    328349<code>SDST = 0
    329350for (UINT8 i = 0; i &lt; 32; i++)
    … …  
    335356Description: Count zero bits in SSRC0 and store result to SDST.
    336357If result is non-zero, store 1 to SCC, otherwise store 0 to SCC. SSRC0 is 64-bit.<br />
     358Operation:<br />
    337359<code>SDST = 0
    338360for (UINT8 i = 0; i &lt; 64; i++)
    … …  
    344366Description: Count one bits in SSRC0 and store result to SDST.
    345367If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.<br />
     368Operation:<br />
    346369<code>SDST = 0
    347370for (UINT8 i = 0; i &lt; 32; i++)
    … …  
    353376Description: Count one bits in SSRC0 and store result to SDST.
    354377If result is non-zero, store 1 to SCC, otherwise store 0 to SCC. SSRC0 is 64-bit.<br />
     378Operation:<br />
    355379<code>SDST = 0
    356380for (UINT8 i = 0; i &lt; 64; i++)
    357381    SDST += ((1ULL&lt;&lt;i) &amp; SSRC0) != 0
    358382SCC = SDST!=0</code></p>
     383<h4>S_BITSET0_B32</h4>
     384<p>Opcode: 27 (0x1b) for GCN 1.0/1.1, 24 (0x18) for GCN 1.2<br />
     385Syntax: S_BITSET0_B32 SDST, SSRC0<br />
     386Description: Get value from SDST, clear its bit with number specified from SSRC0, and
     387store result to SDST.<br />
     388Operation:<br />
     389<code>SDST &amp;= ~(1U &lt;&lt; (SSRC0&amp;31))</code></p>
     390<h4>S_BITSET0_B64</h4>
     391<p>Opcode: 28 (0x1c) for GCN 1.0/1.1, 25 (0x19) for GCN 1.2<br />
     392Syntax: S_BITSET0_B64 SDST(2), SSRC0<br />
     393Description: Get value from SDST, clear its bit with number specified from SSRC0, and
     394store result to SDST. SDST is 64-bit.<br />
     395Operation:<br />
     396<code>SDST &amp;= ~(1ULL &lt;&lt; (SSRC0&amp;63))</code></p>
     397<h4>S_BITSET1_B32</h4>
     398<p>Opcode: 29 (0x1d) for GCN 1.0/1.1, 26 (0x1a) for GCN 1.2<br />
     399Syntax: S_BITSET1_B32 SDST, SSRC0<br />
     400Description: Get value from SDST, set its bit with number specified from SSRC0, and
     401store result to SDST.<br />
     402Operation:<br />
     403<code>SDST |= 1U &lt;&lt; (SSRC0&amp;31)</code></p>
     404<h4>S_BITSET1_B64</h4>
     405<p>Opcode: 30 (0x1e) for GCN 1.0/1.1, 27 (0x1c) for GCN 1.2<br />
     406Syntax: S_BITSET1_B64 SDST(2), SSRC0<br />
     407Description: Get value from SDST, set its bit with number specified from SSRC0, and
     408store result to SDST. SDST is 64-bit.<br />
     409Operation:<br />
     410<code>SDST |= 1ULL &lt;&lt; (SSRC0&amp;63)</code></p>
    359411<h4>S_BREV_B32</h4>
    360412<p>Opcode: 11 (0xb) for GCN 1.0/1.1; 8 (0x8) for GCN 1.2<br />
    361413Syntax: S_BREV_B32 SDST, SSRC0<br />
    362414Description: Reverse bits in SSRC0 and store result to SDST. SCC is not changed.<br />
     415Operation:<br />
    363416<code>SDST = REVBIT(SSRC0)</code></p>
    364417<h4>S_BREV_B64</h4>
    … …  
    367420Description: Reverse bits in SSRC0 and store result to SDST. SCC is not changed.
    368421SDST and SSRC0 are 64-bit.<br />
     422Operation:<br />
    369423<code>SDST = REVBIT(SSRC0)</code></p>
    370424<h4>S_CMOV_B32</h4>
    … …  
    385439<p>Opcode: 17 (0x11) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2<br />
    386440Syntax: S_FF0_I32_B32 SDST, SSRC0<br />
    387 Description: Find first zero bit in SSRC0. If found store number of bit to SDST,
     441Description: Find first zero bit in SSRC0. If found, store number of bit to SDST,
    388442otherwise set SDST to -1.<br />
     443Operation:<br />
    389444<code>SDST = -1
    390445for (UINT8 i = 0; i &lt; 32; i++)
    … …  
    394449<p>Opcode: 18 (0x12) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2<br />
    395450Syntax: S_FF0_I32_B64 SDST, SSRC0(2)<br />
    396 Description: Find first zero bit in SSRC0. If found store number of bit to SDST,
     451Description: Find first zero bit in SSRC0. If found, store number of bit to SDST,
    397452otherwise set SDST to -1. SSRC0 is 64-bit.<br />
     453Operation:<br />
    398454<code>SDST = -1
    399455for (UINT8 i = 0; i &lt; 64; i++)
    … …  
    403459<p>Opcode: 19 (0x13) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2<br />
    404460Syntax: S_FF1_I32_B32 SDST, SSRC0<br />
    405 Description: Find first one bit in SSRC0. If found store number of bit to SDST,
     461Description: Find first one bit in SSRC0. If found, store number of bit to SDST,
    406462otherwise set SDST to -1.<br />
     463Operation:<br />
    407464<code>SDST = -1
    408465for (UINT8 i = 0; i &lt; 32; i++)
    … …  
    412469<p>Opcode: 20 (0x14) for GCN 1.0/1.1; 17 (0x11) for GCN 1.2<br />
    413470Syntax: S_FF0_I32_B64 SDST, SSRC0(2)<br />
    414 Description: Find first one bit in SSRC0. If found store number of bit to SDST,
     471Description: Find first one bit in SSRC0. If found, store number of bit to SDST,
    415472otherwise set SDST to -1. SSRC0 is 64-bit.<br />
     473Operation:<br />
    416474<code>SDST = -1
    417475for (UINT8 i = 0; i &lt; 64; i++)
    … …  
    421479<p>Opcode: 21 (0x15) for GCN 1.0/1.1; 18 (0x12) for GCN 1.2<br />
    422480Syntax: S_FLBIT_I32_B32 SDST, SSRC0<br />
    423 Description: Find last one bit in SSRC0. If found store number of skipped bits to SDST,
     481Description: Find last one bit in SSRC0. If found, store number of skipped bits to SDST,
    424482otherwise set SDST to -1.<br />
     483Operation:<br />
    425484<code>SDST = -1
    426485for (INT8 i = 31; i &gt;= 0; i++)
    … …  
    430489<p>Opcode: 22 (0x16) for GCN 1.0/1.1; 19 (0x13) for GCN 1.2<br />
    431490Syntax: S_FLBIT_I32_B64 SDST, SSRC0(2)<br />
    432 Description: Find last one bit in SSRC0. If found store number of skipped bits to SDST,
    433 otherwise set SDST to -1.  SSRC0 is 64-bit<br />
     491Description: Find last one bit in SSRC0. If found, store number of skipped bits to SDST,
     492otherwise set SDST to -1.  SSRC0 is 64-bit.<br />
     493Operation:<br />
    434494<code>SDST = -1
    435495for (INT8 i = 63; i &gt;= 0; i++)
    436496    if ((1ULL&lt;&lt;i) &amp; SSRC0) != 0)
    437497    { SDST = 63-i; break; }</code></p>
     498<h4>S_FLBIT_I32</h4>
     499<p>Opcode: 23 (0x17) for GCN 1.0/1.1; 20 (0x14) for GCN 1.2<br />
     500Syntax: S_FLBIT_I32 SDST, SSRC0<br />
     501Description: Find last opposite bit to sign in SSRC0. If found, store number of skipped bits
     502to SDST, otherwise set SDST to -1.<br />
     503Operation:<br />
     504<code>SDST = -1
     505UINT32 bitval = (INT32)SSRC0&gt;=0 ? 1 : 0
     506for (INT8 i = 31; i &gt;= 0; i++)
     507    if ((1U&lt;&lt;i) &amp; SSRC0) == (bitval&lt;&lt;i))
     508    { SDST = 31-i; break; }</code></p>
     509<h4>S_FLBIT_I32_I64</h4>
     510<p>Opcode: 24 (0x18) for GCN 1.0/1.1; 21 (0x15) for GCN 1.2<br />
     511Syntax: S_FLBIT_I32_I64 SDST, SSRC0(2)<br />
     512Description: Find last opposite bit to sign in SSRC0. If found, store number of skipped bits
     513to SDST, otherwise set SDST to -1. SSRC0 is 64-bit.<br />
     514Operation:<br />
     515<code>SDST = -1
     516UINT64 bitval = (INT64)SSRC0&gt;=0 ? 1 : 0
     517for (INT8 i = 63; i &gt;= 0; i++)
     518    if ((1U&lt;&lt;i) &amp; SSRC0) == (bitval&lt;&lt;i))
     519    { SDST = 63-i; break; }</code></p>
     520<h4>S_GETPC_B64</h4>
     521<p>Opcode: 31 (0x1f) for GCN 1.0/1.1; 28 (0x1c) for GCN 1.2<br />
     522Syntax: S_GETPC_B64 SDST(2)<br />
     523Description: Store program counter (PC) for next instruction to SDST. SDST is 64-bit.<br />
     524Operation:<br />
     525<code>SDST = PC + 4</code></p>
    438526<h4>S_MOV_B32</h4>
    439527<p>Opcode: 3 (0x3) for GCN 1.0/1.1; 0 (0x0) for GCN 1.2<br />
    … …  
    454542Operation:<br />
    455543<code>SDST = SSRC0</code></p>
     544<h4>S_MOVRELS_B32</h4>
     545<p>Opcode: 46 (0x2e) for GCN 1.0/1.1; 42 (0x2a) for GCN 1.2<br />
     546Syntax: S_MOVRELS_B32 SDST, SSRC0<br />
     547Description: Store value from SGPR[M0+SSRC0_NUMBER] to SDST.
     548SSRC0_NUMBER is number of SDST register.<br />
     549Operation:<br />
     550<code>SDST = SGPR[SSRC0_NUMBER + M0]</code></p>
     551<h4>S_MOVRELS_B64</h4>
     552<p>Opcode: 47 (0x2f) for GCN 1.0/1.1; 43 (0x2b) for GCN 1.2<br />
     553Syntax: S_MOVRELS_B64 SDST, SSRC0<br />
     554Description: Store 64-bit value from SGPR[M0+SSRC0_NUMBER:M0+SSRC0_NUMBER+1] to SDST.
     555SSRC0_NUMBER is number of SDST register.<br />
     556Operation:<br />
     557<code>SDST = SGPR[SSRC0_NUMBER + M0]</code></p>
    456558<h4>S_NOT_B32</h4>
    457559<p>Opcode: 7 (0x7) for GCN 1.0/1.1; 4 (0x4) for GCN 1.2<br />
    … …  
    462564<code>SDST = ~SSRC0
    463565SCC = SDST!=0</code></p>
     566<h4>S_NAND_SAVEEXEC_B64</h4>
     567<p>Opcode: 41 (0x29) for GCN 1.0/1.1; 37 (0x25) for GCN 1.2<br />
     568Syntax: S_NAND_SAVEEXEC_B64 SDST(2), SDST(2)<br />
     569Description: Store EXEC register to SDST. Make bitwise NAND on SSRC0 and EXEC
     570and store result to EXEC. If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
     571SDST and SSRC0 are 64-bit.<br />
     572Operation:<br />
     573<code>SDST = EXEC
     574EXEC = ~(SSRC0 &amp; EXEC)
     575SCC = EXEC!=0</code></p>
     576<h4>S_NOR_SAVEEXEC_B64</h4>
     577<p>Opcode: 42 (0x2a) for GCN 1.0/1.1; 38 (0x26) for GCN 1.2<br />
     578Syntax: S_NOR_SAVEEXEC_B64 SDST(2), SDST(2)<br />
     579Description: Store EXEC register to SDST. Make bitwise NOR on SSRC0 and EXEC
     580and store result to EXEC. If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
     581SDST and SSRC0 are 64-bit.<br />
     582Operation:<br />
     583<code>SDST = EXEC
     584EXEC = ~(SSRC0 | EXEC)
     585SCC = EXEC!=0</code></p>
    464586<h4>S_NOT_B64</h4>
    465587<p>Opcode: 8 (0x8) for GCN 1.0/1.1; 5 (0x5) for GCN 1.2<br />
    … …  
    471593<code>SDST = ~SSRC0
    472594SCC = SDST!=0</code></p>
     595<h4>S_OR_SAVEEXEC_B64</h4>
     596<p>Opcode: 37 (0x25) for GCN 1.0/1.1; 33 (0x21) for GCN 1.2<br />
     597Syntax: S_OR_SAVEEXEC_B64 SDST(2), SDST(2)<br />
     598Description: Store EXEC register to SDST. Make bitwise OR on SSRC0 and EXEC
     599and store result to EXEC. If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
     600SDST and SSRC0 are 64-bit.<br />
     601Operation:<br />
     602<code>SDST = EXEC
     603EXEC = SSRC0 | EXEC
     604SCC = EXEC!=0</code></p>
     605<h4>S_ORN2_SAVEEXEC_B64</h4>
     606<p>Opcode: 40 (0x28) for GCN 1.0/1.1; 36 (0x24) for GCN 1.2<br />
     607Syntax: S_ORN2_SAVEEXEC_B64 SDST(2), SDST(2)<br />
     608Description: Store EXEC register to SDST. Make bitwise OR on SSRC0 and negated EXEC
     609and store result to EXEC. If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
     610SDST and SSRC0 are 64-bit.<br />
     611Operation:<br />
     612<code>SDST = EXEC
     613EXEC = SSRC0 &amp; ~EXEC
     614SCC = EXEC!=0</code></p>
     615<h4>S_QUADMASK_B32</h4>
     616<p>Opcode: 44 (0x2c) for GCN 1.0/1.1; 40 (0x28) for GCN 1.2<br />
     617Syntax: S_QUADMASK_B32 SDST, SSRC0<br />
     618Description: For every 4-bit groups in SSRC0, if any bit of that group is set, then
     619set bit for that group in order, otherwise clear that bits; and store that result into SDST.
     620If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.<br />
     621Operation:<br />
     622<code>UINT32 temp = 0
     623for (UINT8 i = 0; i &lt; 8; i++)
     624    temp |= ((SSRC0&gt;&gt;(i&lt;&lt;2)) &amp; 15)!=0 ? (1U&lt;&lt;i) : 0
     625SDST = temp
     626SCC = SDST!=0</code></p>
     627<h4>S_QUADMASK_B64</h4>
     628<p>Opcode: 45 (0x2d) for GCN 1.0/1.1; 41 (0x29) for GCN 1.2<br />
     629Syntax: S_QUADMASK_B64 SDST(2), SSRC0(2)<br />
     630Description: For every 4-bit groups in SSRC0, if any bit of that group is set, then
     631set bit for that group in order, otherwise clear that bits; and store that result into SDST.
     632If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
     633SDST and SSRC0 are 64-bit.<br />
     634Operation:<br />
     635<code>UINT64 temp = 0
     636for (UINT8 i = 0; i &lt; 16; i++)
     637    temp |= ((SSRC0&gt;&gt;(i&lt;&lt;2)) &amp; 15)!=0 ? (1U&lt;&lt;i) : 0
     638SDST = temp
     639SCC = SDST!=0</code></p>
     640<h4>S_RFE_B64</h4>
     641<p>Opcode: 34 (0x22) for GCN 1.0/1.1; 31 (0x1f) for GCN 1.2<br />
     642Syntac: S_RFE_B64 SSRC0(2)<br />
     643Description: Return from exception (store TTMP[0:1] to PC ???).<br />
     644Operation: ???<br />
     645<code>PC = TTMP[0:1]</code></p>
     646<h4>S_SETPC_B64</h4>
     647<p>Opcode: 32 (0x20) for GCN 1.0/1.1; 29 (0x1d) for GCN 1.2<br />
     648Syntax: S_SETPC_B64 SSRC0(2)<br />
     649Description: Jump to address given SSRC0 (store SSRC0 to PC). SSRC0 is 64-bit.<br />
     650Operation:<br />
     651<code>PC = SSRC0</code></p>
     652<h4>S_SEXT_I32_I8</h4>
     653<p>Opcode: 25 (0x19) for GCN 1.0/1.1; 22 (0x16) for GCN 1.2<br />
     654Syntax: S_SEXT_I32_I8 SDST, SSRC0<br />
     655Description: Store signed extended 8-bit value from SSRC0 to SDST.<br />
     656Operation:<br />
     657<code>SDST = SEXT((INT8)SSRC0)</code></p>
     658<h4>S_SEXT_I32_I16</h4>
     659<p>Opcode: 26 (0x1a) for GCN 1.0/1.1; 23 (0x17) for GCN 1.2<br />
     660Syntax: S_SEXT_I32_I16 SDST, SSRC0<br />
     661Description: Store signed extended 16-bit value from SSRC0 to SDST.<br />
     662Operation:<br />
     663<code>SDST = SEXT((INT16)SSRC0)</code></p>
     664<h4>S_SWAPPC_B64</h4>
     665<p>Opcode: 33 (0x21) for GCN 1.0/1.1; 30 (0x1e) for GCN 1.2<br />
     666Syntax: S_SWAPPC_B64 SDST(2), SSRC0(2)<br />
     667Description: Store program counter to SDST and jump to address given SSRC0
     668(store SSRC0 to PC). SDST and SSRC0 are 64-bit.<br />
     669Operation:<br />
     670<code>SDST = PC + 4
     671PC = SSRC0</code></p>
    473672<h4>S_WQM_B32</h4>
    474673<p>Opcode: 9 (0x9) for GCN 1.0/1.1; 6 (0x6) for GCN 1.2<br />
    … …  
    478677If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.<br />
    479678Operation:<br />
    480 <code>UINT32 temp
     679<code>UINT32 temp = 0
    481680for (UINT8 i = 0; i &lt; 32; i+=4)
    482681    temp |= ((SSRC0&gt;&gt;i) &amp; 15)!=0 ? (15&lt;&lt;i) : 0
    … …  
    491690SDST and SSRC0 are 64-bit.<br />
    492691Operation:<br />
    493 <code>UINT64 temp
     692<code>UINT64 temp = 0
    494693for (UINT8 i = 0; i &lt; 64; i+=4)
    495694    temp |= ((SSRC0&gt;&gt;i) &amp; 15)!=0 ? (15ULL&lt;&lt;i) : 0
    496695SDST = temp
    497696SCC = SDST!=0</code></p>
     697<h4>S_XNOR_SAVEEXEC_B64</h4>
     698<p>Opcode: 43 (0x2b) for GCN 1.0/1.1; 39 (0x27) for GCN 1.2<br />
     699Syntax: S_XNOR_SAVEEXEC_B64 SDST(2), SDST(2)<br />
     700Description: Store EXEC register to SDST. Make bitwise XNOR on SSRC0 and EXEC
     701and store result to EXEC. If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
     702SDST and SSRC0 are 64-bit.<br />
     703Operation:<br />
     704<code>SDST = EXEC
     705EXEC = ~(SSRC0 ^ EXEC)
     706SCC = EXEC!=0</code></p>
     707<h4>S_XOR_SAVEEXEC_B64</h4>
     708<p>Opcode: 38 (0x26) for GCN 1.0/1.1; 34 (0x22) for GCN 1.2<br />
     709Syntax: S_XOR_SAVEEXEC_B64 SDST(2), SDST(2)<br />
     710Description: Store EXEC register to SDST. Make bitwise XOR on SSRC0 and EXEC
     711and store result to EXEC. If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
     712SDST and SSRC0 are 64-bit.<br />
     713Operation:<br />
     714<code>SDST = EXEC
     715EXEC = SSRC0 ^ EXEC
     716SCC = EXEC!=0</code></p>
    498717}}}