Changes between Version 6 and Version 7 of GcnInstrsSop2


Ignore:
Timestamp:
11/14/15 00:00:17 (8 years ago)
Author:
trac
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • GcnInstrsSop2

    v6 v7  
    4848<tr>
    4949<th>Opcode</th>
    50 <th>Mnemonic</th>
     50<th>Mnemonic (GCN1.0/1.1)</th>
     51<th>Mnemonic (GCN 1.2)</th>
    5152</tr>
    5253</thead>
    5354<tbody>
    5455<tr>
    55 <td>0</td>
     56<td>0 (0x0)</td>
    5657<td>S_ADD_U32</td>
    57 </tr>
    58 <tr>
    59 <td>1</td>
     58<td>S_ADD_U32</td>
     59</tr>
     60<tr>
     61<td>1 (0x1)</td>
    6062<td>S_SUB_U32</td>
    61 </tr>
    62 <tr>
    63 <td>2</td>
     63<td>S_SUB_U32</td>
     64</tr>
     65<tr>
     66<td>2 (0x2)</td>
    6467<td>S_ADD_I32</td>
    65 </tr>
    66 <tr>
    67 <td>3</td>
     68<td>S_ADD_I32</td>
     69</tr>
     70<tr>
     71<td>3 (0x3)</td>
    6872<td>S_SUB_I32</td>
    69 </tr>
    70 <tr>
    71 <td>4</td>
     73<td>S_SUB_I32</td>
     74</tr>
     75<tr>
     76<td>4 (0x4)</td>
    7277<td>S_ADDC_U32</td>
    73 </tr>
    74 <tr>
    75 <td>5</td>
     78<td>S_ADDC_U32</td>
     79</tr>
     80<tr>
     81<td>5 (0x5)</td>
    7682<td>S_SUBB_U32</td>
    77 </tr>
    78 <tr>
    79 <td>6</td>
     83<td>S_SUBB_U32</td>
     84</tr>
     85<tr>
     86<td>6 (0x6)</td>
    8087<td>S_MIN_I32</td>
    81 </tr>
    82 <tr>
    83 <td>7</td>
     88<td>S_MIN_I32</td>
     89</tr>
     90<tr>
     91<td>7 (0x7)</td>
    8492<td>S_MIN_U32</td>
    85 </tr>
    86 <tr>
    87 <td>8</td>
     93<td>S_MIN_U32</td>
     94</tr>
     95<tr>
     96<td>8 (0x8)</td>
    8897<td>S_MAX_I32</td>
    89 </tr>
    90 <tr>
    91 <td>9</td>
     98<td>S_MAX_I32</td>
     99</tr>
     100<tr>
     101<td>9 (0x9)</td>
    92102<td>S_MAX_U32</td>
    93 </tr>
    94 <tr>
    95 <td>10</td>
     103<td>S_MAX_U32</td>
     104</tr>
     105<tr>
     106<td>10 (0xa)</td>
    96107<td>S_CSELECT_B32</td>
    97 </tr>
    98 <tr>
    99 <td>11</td>
     108<td>S_CSELECT_B32</td>
     109</tr>
     110<tr>
     111<td>11 (0xb)</td>
    100112<td>S_CSELECT_B64</td>
    101 </tr>
    102 <tr>
    103 <td>14</td>
     113<td>S_CSELECT_B64</td>
     114</tr>
     115<tr>
     116<td>12 (0xc)</td>
     117<td>--</td>
    104118<td>S_AND_B32</td>
    105119</tr>
    106120<tr>
    107 <td>15</td>
     121<td>13 (0xd)</td>
     122<td>--</td>
    108123<td>S_AND_B64</td>
    109124</tr>
    110125<tr>
    111 <td>16</td>
     126<td>14 (0xe)</td>
     127<td>S_AND_B32</td>
    112128<td>S_OR_B32</td>
    113129</tr>
    114130<tr>
    115 <td>17</td>
     131<td>15 (0xf)</td>
     132<td>S_AND_B64</td>
    116133<td>S_OR_B64</td>
    117134</tr>
    118135<tr>
    119 <td>18</td>
     136<td>16 (0x10)</td>
     137<td>S_OR_B32</td>
    120138<td>S_XOR_B32</td>
    121139</tr>
    122140<tr>
    123 <td>19</td>
     141<td>17 (0x11)</td>
     142<td>S_OR_B64</td>
    124143<td>S_XOR_B64</td>
     144</tr>
     145<tr>
     146<td>18 (0x12)</td>
     147<td>S_XOR_B32</td>
     148<td>S_ANDN2_B32</td>
     149</tr>
     150<tr>
     151<td>19 (0x13)</td>
     152<td>S_XOR_B64</td>
     153<td>S_ANDN2_B64</td>
     154</tr>
     155<tr>
     156<td>20 (0x14)</td>
     157<td>S_ANDN2_B32</td>
     158<td>S_ORN2_B32</td>
     159</tr>
     160<tr>
     161<td>21 (0x15)</td>
     162<td>S_ANDN2_B64</td>
     163<td>S_ORN2_B64</td>
     164</tr>
     165<tr>
     166<td>22 (0x16)</td>
     167<td>S_ORN2_B32</td>
     168<td>S_NAND_B32</td>
     169</tr>
     170<tr>
     171<td>23 (0x17)</td>
     172<td>S_ORN2_B64</td>
     173<td>S_NAND_B64</td>
     174</tr>
     175<tr>
     176<td>24 (0x18)</td>
     177<td>S_NAND_B32</td>
     178<td>S_NOR_B32</td>
     179</tr>
     180<tr>
     181<td>25 (0x19)</td>
     182<td>S_NAND_B64</td>
     183<td>S_NOR_B64</td>
     184</tr>
     185<tr>
     186<td>26 (0x1a)</td>
     187<td>S_NOR_B32</td>
     188<td>S_XNOR_B32</td>
     189</tr>
     190<tr>
     191<td>27 (0x1b)</td>
     192<td>S_NOR_B64</td>
     193<td>S_XNOR_B64</td>
     194</tr>
     195<tr>
     196<td>28 (0x1c)</td>
     197<td>S_XNOR_B32</td>
     198<td>S_LSHL_B32</td>
     199</tr>
     200<tr>
     201<td>29 (0x1d)</td>
     202<td>S_XNOR_B64</td>
     203<td>S_LSHL_B64</td>
     204</tr>
     205<tr>
     206<td>30 (0x1e)</td>
     207<td>S_LSHL_B32</td>
     208<td>S_LSHR_B32</td>
     209</tr>
     210<tr>
     211<td>31 (0x1f)</td>
     212<td>S_LSHL_B64</td>
     213<td>S_LSHR_B64</td>
     214</tr>
     215<tr>
     216<td>32 (0x20)</td>
     217<td>S_LSHR_B32</td>
     218<td>S_ASHR_I32</td>
     219</tr>
     220<tr>
     221<td>33 (0x21)</td>
     222<td>S_LSHR_B64</td>
     223<td>S_ASHR_I64</td>
     224</tr>
     225<tr>
     226<td>34 (0x22)</td>
     227<td>S_ASHR_I32</td>
     228<td>S_BFM_B32</td>
     229</tr>
     230<tr>
     231<td>35 (0x23)</td>
     232<td>S_ASHR_I64</td>
     233<td>S_BFM_B64</td>
     234</tr>
     235<tr>
     236<td>36 (0x24)</td>
     237<td>S_BFM_B32</td>
     238<td>S_MUL_I32</td>
     239</tr>
     240<tr>
     241<td>37 (0x25)</td>
     242<td>S_BFM_B64</td>
     243<td>S_BFE_U32</td>
     244</tr>
     245<tr>
     246<td>38 (0x26)</td>
     247<td>S_MUL_I32</td>
     248<td>S_BFE_I32</td>
     249</tr>
     250<tr>
     251<td>39 (0x27)</td>
     252<td>S_BFE_U32</td>
     253<td>S_BFE_U64</td>
     254</tr>
     255<tr>
     256<td>40 (0x28)</td>
     257<td>S_BFE_I32</td>
     258<td>S_BFE_I64</td>
     259</tr>
     260<tr>
     261<td>41 (0x29)</td>
     262<td>S_BFE_U64</td>
     263<td>S_CBRANCH_G_FORK</td>
     264</tr>
     265<tr>
     266<td>42 (0x2a)</td>
     267<td>S_BFE_I64</td>
     268<td>S_ABSDIFF_I32</td>
     269</tr>
     270<tr>
     271<td>43 (0x2b)</td>
     272<td>S_CBRANCH_G_FORK</td>
     273<td>S_RFE_RESTORE_B64</td>
     274</tr>
     275<tr>
     276<td>44 (0x2c)</td>
     277<td>S_ABSDIFF_I32</td>
     278<td>--</td>
    125279</tr>
    126280</tbody>
    … …  
    129283<p>Alphabetically sorted instruction list:</p>
    130284<h4>S_ABSDIFF_I32</h4>
    131 <p>Opcode: 44 (0x2c)<br />
     285<p>Opcode: 44 (0x2c) for GCN 1.0/11; 42 (0x2a) for GCN 1.2 <br />
    132286Syntax: S_ABSDIFF_I32 SDST, SSRC0, SSRC1<br />
    133287Description: Compute absolute difference from SSRC0 and SSRC1 and store result to SDST.
    … …  
    162316SCC = temp &gt;&gt; 32</code></p>
    163317<h4>S_AND_B32</h4>
    164 <p>Opcode: 14 (0xe)<br />
     318<p>Opcode: 14 (0xe) for GCN 1.0/1.1; 12 (0xc) for GCN 1.2<br />
    165319Syntax: S_AND_B32 SDST, SSRC0, SSRC1<br />
    166320Description: Do bitwise AND operation on SSRC0 and SSRC1 and store it to SDST, and store
    … …  
    170324SCC = SDST!=0</code></p>
    171325<h4>S_AND_B64</h4>
    172 <p>Opcode: 15 (0xf)<br />
     326<p>Opcode: 15 (0xf) for GCN 1.0/1.1; 13 (0xd) for GCN 1.2<br />
    173327Syntax: S_AND_B64 SDST(2), SSRC0(2), SSRC1(2)<br />
    174328Description: Do bitwise AND operation on SSRC0 and SSRC1 and store it to SDST, and store
    … …  
    178332SCC = SDST!=0</code></p>
    179333<h4>S_ANDN2_B32</h4>
    180 <p>Opcode: 20 (0x14)<br />
     334<p>Opcode: 20 (0x14) for GCN 1.0/1.1; 18 (0x12) for GCN 1.2<br />
    181335Syntax: S_ANDN2_B32 SDST, SSRC0, SSRC1<br />
    182336Description: Do bitwise AND operation on SSRC0 and negated SSRC1 and store it to SDST,
    … …  
    186340SCC = SDST!=0</code></p>
    187341<h4>S_ANDN2_B64</h4>
    188 <p>Opcode: 21 (0x15)<br />
     342<p>Opcode: 21 (0x15) for GCN 1.0/1.1; 19 (0x13) for GCN 1.2<br />
    189343Syntax: S_ANDN2_B64 SDST(2), SSRC0(2), SSRC1(2)<br />
    190344Description: Do bitwise AND operation on SSRC0 and bitwise negated SSRC1 and store
    … …  
    195349SCC = SDST!=0</code></p>
    196350<h4>S_ASHR_I32</h4>
    197 <p>Opcode: 34 (0x22)
     351<p>Opcode: 34 (0x22) for GCN 1.0/1.1; 32 (0x20) for GCN 1.2<br />
    198352Syntax: S_ASHR_I32 SDST, SSRC0, SSRC1<br />
    199353Description: Arithmetic shift to right SSRC0 by (SSRC1&amp;31) bits and store result into SDST.
    … …  
    203357SCC = SDST!=0</code></p>
    204358<h4>S_ASHR_I64</h4>
    205 <p>Opcode: 35 (0x23)<br />
     359<p>Opcode: 35 (0x23) for GCN 1.0/1.1; 33 (0x21) for GCN 1.2<br />
    206360Syntax: S_ASHR_I64 SDST(2), SSRC0(2), SSRC1<br />
    207361Description: Arithmetic Shift to right SSRC0 by (SSRC1&amp;63) bits and store result into SDST.
    … …  
    212366SCC = SDST!=0</code></p>
    213367<h4>S_BFE_I32</h4>
    214 <p>Opcode: 40 (0x28)<br />
     368<p>Opcode: 40 (0x28) for GCN 1.0/1.1; 38 (0x26) for GCN 1.2<br />
    215369Syntax: S_BFE_I32 SDST, SSRC0, SSRC1<br />
    216370Description: Extracts bits in SSRC0 from range (SSRC1&amp;31) with length ((SSRC1&gt;&gt;16)&amp;0x7f)
    … …  
    228382SCC = SDST!=0</code></p>
    229383<h4>S_BFE_U32</h4>
    230 <p>Opcode: 39 (0x27)<br />
     384<p>Opcode: 39 (0x27) for GCN 1.0/1.1; 37 (0x25) for GCN 1.2<br />
    231385Syntax: S_BFE_U32 SDST, SSRC0, SSRC1<br />
    232386Description: Extracts bits in SSRC0 from range (SSRC1&amp;31) with length ((SSRC1&gt;&gt;16)&amp;0x7f).
    … …  
    243397SCC = SDST!=0</code></p>
    244398<h4>S_BFE_I64</h4>
    245 <p>Opcode: 42 (0x2a)<br />
     399<p>Opcode: 42 (0x2a) for GCN 1.0/1.1; 40 (0x28) for GCN 1.2<br />
    246400Syntax: S_BFE_I64 SDST, SSRC0, SSRC1<br />
    247401Description: Extracts bits in SSRC0 from range (SSRC1&amp;63) with length ((SSRC1&gt;&gt;16)&amp;0x7f)
    … …  
    259413SCC = SDST!=0</code></p>
    260414<h4>S_BFE_U64</h4>
    261 <p>Opcode: 41 (0x29)<br />
     415<p>Opcode: 41 (0x29) for GCN 1.0/1.1; 39 (0x27) for GCN 1.2<br />
    262416Syntax: S_BFE_U64 SDST(2), SSRC0(2), SSRC1<br />
    263417Description: Extracts bits in SSRC0 from range (SSRC1&amp;63) with length ((SSRC1&gt;&gt;16)&amp;0x7f).
    … …  
    275429SCC = SDST!=0</code></p>
    276430<h4>S_BFM_B32</h4>
    277 <p>Opcode: 36 (0x24)
     431<p>Opcode: 36 (0x24) for GCN 1.0/1.1; 34 (0x22) for GCN 1.2<br />
    278432Syntax: S_BFM_B32 SDST, SSRC0, SSRC1<br />
    279433Description: Make 32-bit bitmask from (SSRC1 &amp; 31) bit that have length (SSRC0 &amp; 31) and
    … …  
    282436<code>SDST = ((1U &lt;&lt; (SSRC0&amp;31))-1) &lt;&lt; (SSRC1&amp;31)</code></p>
    283437<h4>S_BFM_B64</h4>
    284 <p>Opcode: 37 (0x25)
     438<p>Opcode: 37 (0x25) for GCN 1.0/1.1; 35 (0x23) for GCN 1.2<br />
    285439Syntax: S_BFM_B64 SDST(2), SSRC0, SSRC1<br />
    286440Description: Make 64-bit bitmask from (SSRC1 &amp; 63) bit that have length (SSRC0 &amp; 63) and
    … …  
    303457<code>SDST = SCC ? SSRC0 : SSRC1</code></p>
    304458<h4>S_LSHL_B32</h4>
    305 <p>Opcode: 30 (0x1e)
     459<p>Opcode: 30 (0x1e) for GCN 1.0/1.1; 28 (0x1c) for GCN 1.2<br />
    306460Syntax: S_LSHL_B32 SDST, SSRC0, SSRC1<br />
    307461Description: Shift to left SSRC0 by (SSRC1&amp;31) bits and store result into SDST.
    … …  
    311465SCC = SDST!=0</code></p>
    312466<h4>S_LSHL_B64</h4>
    313 <p>Opcode: 31 (0x1f)
     467<p>Opcode: 31 (0x1f) for GCN 1.0/1.1; 29 (0x1d) for GCN 1.2<br />
    314468Syntax: S_LSHL_B64 SDST(2), SSRC0(2), SSRC1<br />
    315469Description: Shift to left SSRC0 by (SSRC1&amp;63) bits and store result into SDST.
    … …  
    320474SCC = SDST!=0</code></p>
    321475<h4>S_LSHR_B32</h4>
    322 <p>Opcode: 32 (0x20)
     476<p>Opcode: 32 (0x20) for GCN 1.0/1.1; 30 (0x1e) for GCN 1.2<br />
    323477Syntax: S_LSHR_B32 SDST, SSRC0, SSRC1<br />
    324478Description: Shift to right SSRC0 by (SSRC1&amp;31) bits and store result into SDST.
    … …  
    328482SCC = SDST!=0</code></p>
    329483<h4>S_LSHR_B64</h4>
    330 <p>Opcode: 33 (0x21)
     484<p>Opcode: 33 (0x21) for GCN 1.0/1.1; 31 (0x1f) for GCN 1.2<br />
    331485Syntax: S_LSHR_B64 SDST(2), SSRC0(2), SSRC1<br />
    332486Description: Shift to right SSRC0 by (SSRC1&amp;63) bits and store result into SDST.
    … …  
    337491SCC = SDST!=0</code></p>
    338492<h4>S_MAX_I32</h4>
    339 <p>Opcode: 8 (0x9)
     493<p>Opcode: 8 (0x8)<br />
    340494Syntax: S_MIN_I32 SDST, SSRC0, SSRC1<br />
    341495Description: Choose largest signed value value from SSRC0 and SSRC1 and store its into SDST,
    … …  
    353507SCC = SSRC0 &gt; SSRC1</code></p>
    354508<h4>S_MIN_I32</h4>
    355 <p>Opcode: 6 (0x6)
     509<p>Opcode: 6 (0x6)<br />
    356510Syntax: S_MIN_I32 SDST, SSRC0, SSRC1<br />
    357511Description: Choose smallest signed value value from SSRC0 and SSRC1 and store its into SDST,
    … …  
    369523SCC = SSRC0 &lt; SSRC1</code></p>
    370524<h4>S_MUL_I32</h4>
    371 <p>Opcode: 38 (0x26)
     525<p>Opcode: 38 (0x26) for GCN 1.0/1.1; 36 (0x24) for GCN 1.2<br />
    372526Syntax: S_MUL_I32 SDST, SSRC0, SSRC1
    373527Description: Multiply SSRC0 and SSRC1 and store result into SDST. Do not change SCC.<br />
    … …  
    375529<code>SDST = SSRC0 * SSRC1</code></p>
    376530<h4>S_NAND_B32</h4>
    377 <p>Opcode: 24 (0x18)<br />
     531<p>Opcode: 24 (0x18) for GCN 1.0/1.1; 22 (0x16) for GCN 1.2<br />
    378532Syntax: S_NAND_B32 SDST, SSRC0, SSRC1<br />
    379533Description: Do bitwise NAND operation on SSRC0 and SSRC1 and store it to SDST, and store
    … …  
    383537SCC = SDST!=0</code></p>
    384538<h4>S_NAND_B64</h4>
    385 <p>Opcode: 25 (0x19)<br />
     539<p>Opcode: 25 (0x19) for GCN 1.0/1.1; 23 (0x17) for GCN 1.2<br />
    386540Syntax: S_NAND_B64 SDST(2), SSRC0(2), SSRC1(2)<br />
    387541Description: Do bitwise NAND operation on SSRC0 and SSRC1 and store it to SDST, and store
    … …  
    391545SCC = SDST!=0</code></p>
    392546<h4>S_NOR_B32</h4>
    393 <p>Opcode: 26 (0x1a)<br />
     547<p>Opcode: 26 (0x1a) for GCN 1.0/1.1; 24 (0x18) for GCN 1.2<br />
    394548Syntax: S_NOR_B32 SDST, SSRC0, SSRC1<br />
    395549Description: Do bitwise NOR operation on SSRC0 and SSRC1 and store it to SDST, and store
    … …  
    399553SCC = SDST!=0</code></p>
    400554<h4>S_NOR_B64</h4>
    401 <p>Opcode: 27 (0x1b)<br />
     555<p>Opcode: 27 (0x1b) for GCN 1.0/1.1; 25 (0x19) for GCN 1.2<br />
    402556Syntax: S_NOR_B64 SDST(2), SSRC0(2), SSRC1(2)<br />
    403557Description: Do bitwise NOR operation on SSRC0 and SSRC1 and store it to SDST, and store
    … …  
    407561SCC = SDST!=0</code></p>
    408562<h4>S_OR_B32</h4>
    409 <p>Opcode: 16 (0x10)<br />
     563<p>Opcode: 16 (0x10) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2<br />
    410564Syntax: S_OR_B32 SDST, SSRC0, SSRC1<br />
    411565Description: Do bitwise OR operation on SSRC0 and SSRC1 and store it to SDST, and store
    … …  
    415569SCC = SDST!=0</code></p>
    416570<h4>S_OR_B64</h4>
    417 <p>Opcode: 17 (0x11)<br />
     571<p>Opcode: 17 (0x11) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2<br />
    418572Syntax: S_OR_B64 SDST(2), SSRC0(2), SSRC1(2)<br />
    419573Description: Do bitwise OR operation on SSRC0 and SSRC1 and store it to SDST, and store
    … …  
    423577SCC = SDST!=0</code></p>
    424578<h4>S_ORN2_B32</h4>
    425 <p>Opcode: 22 (0x16)<br />
     579<p>Opcode: 22 (0x16) for GCN 1.0/1.1; 20 (0x14) for GCN 1.2<br />
    426580Syntax: S_ORN2_B32 SDST, SSRC0, SSRC1<br />
    427581Description: Do bitwise OR operation on SSRC0 and negated SSRC1 and store it to SDST,
    … …  
    431585SCC = SDST!=0</code></p>
    432586<h4>S_ORN2_B64</h4>
    433 <p>Opcode: 23 (0x17)<br />
     587<p>Opcode: 23 (0x17) for GCN 1.0/1.1; 21 (0x15) for GCN 1.2<br />
    434588Syntax: S_ORN2_B64 SDST(2), SSRC0(2), SSRC1(2)<br />
    435589Description: Do bitwise OR operation on SSRC0 and negated SSRC1 and store it to SDST,
    … …  
    467621SCC = (temp&gt;&gt;32)!=0</code></p>
    468622<h4>S_XNOR_B32</h4>
    469 <p>Opcode: 28 (0x1c)<br />
     623<p>Opcode: 28 (0x1c) for GCN 1.0/1.1; 26 (0x1a) for GCN 1.2<br />
    470624Syntax: S_XNOR_B32 SDST, SSRC0, SSRC1<br />
    471625Description: Do bitwise XNOR operation on SSRC0 and SSRC1 and store it to SDST, and store
    … …  
    475629SCC = SDST!=0</code></p>
    476630<h4>S_XNOR_B64</h4>
    477 <p>Opcode: 29 (0x1d)<br />
     631<p>Opcode: 29 (0x1d) for GCN 1.0/1.1; 27 (0x1b) for GCN 1.2<br />
    478632Syntax: S_XNOR_B64 SDST(2), SSRC0(2), SSRC1(2)<br />
    479633Description: Do bitwise XNOR operation on SSRC0 and SSRC1 and store it to SDST, and store
    … …  
    483637SCC = SDST!=0</code></p>
    484638<h4>S_XOR_B32</h4>
    485 <p>Opcode: 18 (0x12)<br />
     639<p>Opcode: 18 (0x12) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2<br />
    486640Syntax: S_XOR_B32 SDST, SSRC0, SSRC1<br />
    487641Description: Do bitwise XOR operation on SSRC0 and SSRC1 and store it to SDST, and store
    … …  
    491645SCC = SDST!=0</code></p>
    492646<h4>S_XOR_B64</h4>
    493 <p>Opcode: 19 (0x13)<br />
     647<p>Opcode: 19 (0x13) for GCN 1.0/1.1; 17 (0x11) for GCN 1.2<br />
    494648Syntax: S_XOR_B64 SDST(2), SSRC0(2), SSRC1(2)<br />
    495649Description: Do bitwise XOR operation on SSRC0 and SSRC1 and store it to SDST, and store