Changes between Version 8 and Version 9 of GcnInstrsSop2

Timestamp:

11/14/15 14:00:27 (8 years ago)

Author:

trac

Comment:

--

GcnInstrsSop2

@@ -41 +41 @@
 </tbody>
 </table>
-<p>Syntax for all instructions: INSTRUCTION SDST, SSRC0, SSRC1</p>
+<p>Syntax for almost instructions: INSTRUCTION SDST, SSRC0, SSRC1</p>
 <p>Example: s_and_b32 s0, s1, s2</p>
 <p>List of the instructions by opcode:</p>
@@ -372 +372 @@
 If result is non-zero store 1 to SCC, otherwise store 0 to SCC.<br />
 Operation:<br />
-<code>UINT8 shift = SSRC1&amp;31
+<code>UINT8 shift = SSRC1 &amp; 31
 UINT8 length = (SSRC1&gt;&gt;16) &amp; 0x7f
 if (length==0)
@@ -380 +380 @@
 else
     SDST = (INT32)SSRC0 &gt;&gt; shift
+SCC = SDST!=0</code></p>
+<h4>S_BFE_I64</h4>
+<p>Opcode: 42 (0x2a) for GCN 1.0/1.1; 40 (0x28) for GCN 1.2<br />
+Syntax: S_BFE_I64 SDST, SSRC0, SSRC1<br />
+Description: Extracts bits in SSRC0 from range (SSRC1&amp;63) with length ((SSRC1&gt;&gt;16)&amp;0x7f)
+and extend sign from last bit of extracted value.
+If result is non-zero store 1 to SCC, otherwise store 0 to SCC.<br />
+Operation:<br />
+<code>UINT8 shift = SSRC1 &amp; 63
+UINT8 length = (SSRC1&gt;&gt;16) &amp; 0x7f
+if (length==0)
+    SDST = 0
+if (shift+length &lt; 64)
+    SDST = (INT64)(SSRC0 &lt;&lt; (64 - shift - length)) &gt;&gt; (64 - length)
+else
+    SDST = (INT64)SSRC0 &gt;&gt; shift
 SCC = SDST!=0</code></p>
 <h4>S_BFE_U32</h4>
@@ -396 +412 @@
     SDST = SSRC0 &gt;&gt; shift
 SCC = SDST!=0</code></p>
-<h4>S_BFE_I64</h4>
-<p>Opcode: 42 (0x2a) for GCN 1.0/1.1; 40 (0x28) for GCN 1.2<br />
-Syntax: S_BFE_I64 SDST, SSRC0, SSRC1<br />
-Description: Extracts bits in SSRC0 from range (SSRC1&amp;63) with length ((SSRC1&gt;&gt;16)&amp;0x7f)
-and extend sign from last bit of extracted value.
-If result is non-zero store 1 to SCC, otherwise store 0 to SCC.<br />
-Operation:<br />
-<code>UINT8 shift = SSRC1&amp;63
-UINT8 length = (SSRC1&gt;&gt;16) &amp; 0x7f
-if (length==0)
-    SDST = 0
-if (shift+length &lt; 64)
-    SDST = (INT64)(SSRC0 &lt;&lt; (64 - shift - length)) &gt;&gt; (64 - length)
-else
-    SDST = (INT64)SSRC0 &gt;&gt; shift
-SCC = SDST!=0</code></p>
 <h4>S_BFE_U64</h4>
 <p>Opcode: 41 (0x29) for GCN 1.0/1.1; 39 (0x27) for GCN 1.2<br />
@@ -442 +442 @@
 Operation:<br />
 <code>SDST = ((1ULL &lt;&lt; (SSRC0&amp;63))-1) &lt;&lt; (SSRC1&amp;63)</code></p>
+<h4>S_CBRANCH_G_FORK</h4>
+<p>Opcode: 43 (0x2b) for GCN 1.0/1.1; 41 (0x29) for GCN 1.2<br />
+Syntax: S_CBRANCH_G_FORK SSRC0(2), SSRC1(2)<br />
+Description: Fork control flow to passed and failed condition, jump to address SSRC1 for
+passed conditions. Make two masks: for passed conditions (EXEC &amp; SSRC0),
+for failed conditions: (EXEC &amp; ~SSRC0).
+Choose way that have smallest active threads and push data for second way to control stack 
+(EXEC mask, jump address). Control stack pointer is stored in CSP
+(3 last bits in MODE register). One entry of the stack have 4 dwords.
+This instruction doesn't work if SSRC0 is immediate value.<br />
+Operation:<br />
+<code>UINT64 passes = (EXEC &amp; SSRC0)
+UINT64 failures = (EXEC &amp; ~SSRC0)
+if (passes == EXEC)
+    PC = SSRC1
+else if (failures == EXEC)
+    PC += 4
+else if (BITCOUNT(failures) &lt; BITCOUNT(passes)) {
+    EXEC = failures
+    SGPR[CSP*4:CSP*4+1] = passes
+    SGPR[CSP*4+2:CSP*4+3] = SSRC1
+    CSP++
+    PC += 4 /* jump to failure */
+} else {
+    EXEC = passes
+    SGPR[CSP*4:CSP*4+1] = failures
+    SGPR[CSP*4+2:CSP*4+3] = PC+4
+    CSP++
+    PC = SSRC1  /* jump to passes */
+}</code></p>
 <h4>S_CSELECT_B32</h4>
 <p>Opcode: 10 (0xa)<br />