| 1111 | <h4>V_CVT_FLR_I32_F32</h4> |
| 1112 | <p>Opcode VOP2: 13 (0xd)<br /> |
| 1113 | Opcode VOP3A: 397 (0x18d) for GCN 1.0/1.1; 333 (0x14d) for GCN 1.2<br /> |
| 1114 | Syntax: V_CVT_FLR_I32_F32 VDST, SRC0<br /> |
| 1115 | Description: Convert 32-bit floating point value from SRC0 to signed 32-bit integer, and |
| 1116 | store result to VDST. Conversion uses rounding to negative infinity (floor). |
| 1117 | If value is higher/lower than maximal/minimal integer then store MAX_INT32/MIN_INT32 to VDST. |
| 1118 | If input value is NaN/-NaN then store MAX_INT32/MIN_INT32 to VDST.<br /> |
| 1119 | Operation:<br /> |
| 1120 | <code>if (ABS(SRC0)!=NAN) |
| 1121 | VDST = (INT32)MAX(MIN(FLOOR(ASFLOAT(SRC0)), 2147483647.0), -2147483648.0) |
| 1122 | else |
| 1123 | VDST = (INT32)SRC0>=0 ? 2147483647 : -2147483648</code></p> |
| 1148 | <h4>V_CVT_RPI_I32_F32</h4> |
| 1149 | <p>Opcode VOP2: 12 (0xc)<br /> |
| 1150 | Opcode VOP3A: 396 (0x18c) for GCN 1.0/1.1; 332 (0x14c) for GCN 1.2<br /> |
| 1151 | Syntax: V_CVT_RPI_I32_F32 VDST, SRC0<br /> |
| 1152 | Description: Convert 32-bit floating point value from SRC0 to signed 32-bit integer, and |
| 1153 | store result to VDST. Conversion adds 0.5 to value and rounds negative infinity (floor). |
| 1154 | If value is higher/lower than maximal/minimal integer then store MAX_INT32/MIN_INT32 to VDST. |
| 1155 | If input value is NaN/-NaN then store MAX_INT32/MIN_INT32 to VDST.<br /> |
| 1156 | Description:<br /> |
| 1157 | <code>if (ABS(SRC0)!=NAN) |
| 1158 | VDST = (INT32)MAX(MIN(FLOOR(ASFLOAT(SRC0) + 0.5), 2147483647.0), -2147483648.0) |
| 1159 | else |
| 1160 | VDST = (INT32)SRC0>=0 ? 2147483647 : -2147483648</code></p> |