Changes between Version 5 and Version 6 of GcnInstrsVop1


Ignore:
Timestamp:
11/28/15 15:00:15 (8 years ago)
Author:
trac
Comment:

--

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  • GcnInstrsVop1

    v5 v6  
    10731073<p>Alphabetically sorted instruction list:</p>
    10741074<h4>V_CVT_F16_F32</h4>
    1075 <p>Opcode VOP2: 10 (0xa)<br />
     1075<p>Opcode VOP1: 10 (0xa)<br />
    10761076Opcode VOP3A: 394 (0x18a) for GCN 1.0/1.1; 330 (0x14a) for GCN 1.2<br />
    10771077Syntax: V_CVT_F16_F32 VDST, SRC0<br />
    … …  
    10801080If absolute value is too high, then store -/+infinity to VDST.<br />
    10811081Operation:<br />
    1082 <code>VDST = RNDHALF(ASFLOAT(SRC0))</code></p>
     1082<code>VDST = CVTHALF(ASFLOAT(SRC0))</code></p>
    10831083<h4>V_CVT_F32_F16</h4>
    1084 <p>Opcode VOP2: 11 (0xb)<br />
     1084<p>Opcode VOP1: 11 (0xb)<br />
    10851085Opcode VOP3A: 395 (0x18b) for GCN 1.0/1.1; 331 (0x14b) for GCN 1.2<br />
    10861086Syntax: V_CVT_F32_F16 VDST, SRC0<br />
    … …  
    10881088Operation:<br />
    10891089<code>VDST = (FLOAT)(ASHALF(SRC0))</code></p>
     1090<h4>V_CVT_F32_F64</h4>
     1091<p>Opcode VOP1: 15 (0xf)<br />
     1092Opcode VOP3A: 399 (0x18f) for GCN 1.0/1.1; 335 (0x14f) for GCN 1.2<br />
     1093Syntax: V_CVT_F32_F64 VDST, SRC0(2)<br />
     1094Description: Convert double FP value to single floating point value with rounding from
     1095MODE register (single FP rounding mode), and store result to VDST.
     1096If absolute value is too high, then store -/+infinity to VDST.<br />
     1097Operation:<br />
     1098<code>VDST = CVTHALF(ASDOUBLE(SRC0))</code></p>
    10901099<h4>V_CVT_F32_I32</h4>
    1091 <p>Opcode VOP2: 5 (0x5)<br />
     1100<p>Opcode VOP1: 5 (0x5)<br />
    10921101Opcode VOP3A: 389 (0x185) for GCN 1.0/1.1; 325 (0x145) for GCN 1.2<br />
    10931102Syntax: V_CVT_F32_I32 VDST, SRC0<br />
    … …  
    10961105<code>VDST = (FLOAT)(INT32)SRC0</code></p>
    10971106<h4>V_CVT_F32_U32</h4>
    1098 <p>Opcode VOP2: 6 (0x6)<br />
     1107<p>Opcode VOP1: 6 (0x6)<br />
    10991108Opcode VOP3A: 390 (0x186) for GCN 1.0/1.1; 326 (0x146) for GCN 1.2<br />
    11001109Syntax: V_CVT_F32_U32 VDST, SRC0<br />
    … …  
    11021111Operation:<br />
    11031112<code>VDST = (FLOAT)SRC0</code></p>
     1113<h4>V_CVT_F32_UBYTE0</h4>
     1114<p>Opcode VOP1: 17 (0x11)<br />
     1115Opcode VOP3A: 401 (0x191) for GCN 1.0/1.1; 337 (0x151) for GCN 1.2<br />
     1116Syntax: V_CVT_F32_UBYTE0 VDST, SRC0<br />
     1117Description: Convert the first unsigned 8-bit byte from SRC0 to single FP value,
     1118and store it to VDST.<br />
     1119Operation:<br />
     1120<code>VDST = (FLOAT)(SRC0 &amp; 0xff)</code></p>
     1121<h4>V_CVT_F32_UBYTE1</h4>
     1122<p>Opcode VOP1: 18 (0x12)<br />
     1123Opcode VOP3A: 402 (0x192) for GCN 1.0/1.1; 338 (0x152) for GCN 1.2<br />
     1124Syntax: V_CVT_F32_UBYTE1 VDST, SRC0<br />
     1125Description: Convert the second unsigned 8-bit byte from SRC0 to single FP value,
     1126and store it to VDST.<br />
     1127Operation:<br />
     1128<code>VDST = (FLOAT)((SRC0&gt;&gt;8) &amp; 0xff)</code></p>
     1129<h4>V_CVT_F32_UBYTE2</h4>
     1130<p>Opcode VOP1: 19 (0x13)<br />
     1131Opcode VOP3A: 403 (0x193) for GCN 1.0/1.1; 339 (0x153) for GCN 1.2<br />
     1132Syntax: V_CVT_F32_UBYTE2 VDST, SRC0<br />
     1133Description: Convert the third unsigned 8-bit byte from SRC0 to single FP value,
     1134and store it to VDST.<br />
     1135Operation:<br />
     1136<code>VDST = (FLOAT)((SRC0&gt;&gt;16) &amp; 0xff)</code></p>
     1137<h4>V_CVT_F32_UBYTE3</h4>
     1138<p>Opcode VOP1: 20 (0x14)<br />
     1139Opcode VOP3A: 404 (0x194) for GCN 1.0/1.1; 340 (0x154) for GCN 1.2<br />
     1140Syntax: V_CVT_F32_UBYTE3 VDST, SRC0<br />
     1141Description: Convert the fourth unsigned 8-bit byte from SRC0 to single FP value,
     1142and store it to VDST.<br />
     1143Operation:<br />
     1144<code>VDST = (FLOAT)(SRC0&gt;&gt;24)</code></p>
     1145<h4>V_CVT_F64_F32</h4>
     1146<p>Opcode VOP1: 16 (0x10)<br />
     1147Opcode VOP3A: 400 (0x190) for GCN 1.0/1.1; 336 (0x150) for GCN 1.2<br />
     1148Syntax: V_CVT_F64_F32 VDST(2), SRC0<br />
     1149Description: Convert single FP value to double FP value, and store result to VDST.<br />
     1150Operation:<br />
     1151<code>VDST = (DOUBLE)(ASFLOAT(SRC0))</code></p>
    11041152<h4>V_CVT_F64_I32</h4>
    1105 <p>Opcode VOP2: 4 (0x4)<br />
     1153<p>Opcode VOP1: 4 (0x4)<br />
    11061154Opcode VOP3A: 388 (0x184) for GCN 1.0/1.1; 324 (0x144) for GCN 1.2<br />
    11071155Syntax: V_CVT_F64_I32 VDST(2), SRC0<br />
    … …  
    11101158<code>VDST = (DOUBLE)(INT32)SRC0</code></p>
    11111159<h4>V_CVT_FLR_I32_F32</h4>
    1112 <p>Opcode VOP2: 13 (0xd)<br />
     1160<p>Opcode VOP1: 13 (0xd)<br />
    11131161Opcode VOP3A: 397 (0x18d) for GCN 1.0/1.1; 333 (0x14d) for GCN 1.2<br />
    11141162Syntax: V_CVT_FLR_I32_F32 VDST, SRC0<br />
    … …  
    11231171    VDST = (INT32)SRC0&gt;=0 ? 2147483647 : -2147483648</code></p>
    11241172<h4>V_CVT_I32_F32</h4>
    1125 <p>Opcode VOP2: 8 (0x8)<br />
     1173<p>Opcode VOP1: 8 (0x8)<br />
    11261174Opcode VOP3A: 392 (0x188) for GCN 1.0/1.1; 328 (0x148) for GCN 1.2<br />
    11271175Syntax: V_CVT_I32_F32 VDST, SRC0<br />
    … …  
    11351183    VDST = (INT32)MAX(MIN(RNDTZINT(ASFLOAT(SRC0)), 2147483647.0), -2147483648.0)</code></p>
    11361184<h4>V_CVT_I32_F64</h4>
    1137 <p>Opcode VOP2: 3 (0x3)<br />
     1185<p>Opcode VOP1: 3 (0x3)<br />
    11381186Opcode VOP3A: 387 (0x183) for GCN 1.0/1.1; 323 (0x143) for GCN 1.2<br />
    11391187Syntax: V_CVT_I32_F64 VDST, SRC0(2)<br />
    … …  
    11461194if (SRC0!=NAN)
    11471195    VDST = (INT32)MAX(MIN(RNDTZINT(ASDOUBLE(SRC0)), 2147483647.0), -2147483648.0)</code></p>
     1196<h4>V_CVT_OFF_F32_I4</h4>
     1197<p>Opcode VOP1: 14 (0xe)<br />
     1198Opcode VOP3A: 398 (0x18e) for GCN 1.0/1.1; 334 (0x14e) for GCN 1.2<br />
     1199Syntax: V_CVT_OFF_F32_I4 VDST, SRC0<br />
     1200Description: Convert 4-bit signed value from SRC0 to floating point value, normalize that
     1201value to range -0.5:0.4375 and store result to VDST.<br />
     1202Operation:<br />
     1203<code>VDST = (FLOAT)((SRC0 &amp; 0xf) ^ 8) / 16.0 - 0.5</code></p>
    11481204<h4>V_CVT_RPI_I32_F32</h4>
    1149 <p>Opcode VOP2: 12 (0xc)<br />
     1205<p>Opcode VOP1: 12 (0xc)<br />
    11501206Opcode VOP3A: 396 (0x18c) for GCN 1.0/1.1; 332 (0x14c) for GCN 1.2<br />
    11511207Syntax: V_CVT_RPI_I32_F32 VDST, SRC0<br />
    … …  
    11601216    VDST = (INT32)SRC0&gt;=0 ? 2147483647 : -2147483648</code></p>
    11611217<h4>V_CVT_U32_F32</h4>
    1162 <p>Opcode VOP2: 7 (0x7)<br />
     1218<p>Opcode VOP1: 7 (0x7)<br />
    11631219Opcode VOP3A: 391 (0x187) for GCN 1.0/1.1; 327 (0x147) for GCN 1.2<br />
    11641220Syntax: V_CVT_U32_F32 VDST, SRC0<br />
    … …  
    11721228    VDST = (UINT32)MIN(RNDTZINT(ASFLOAT(SRC0)), 4294967295.0)</code></p>
    11731229<h4>V_MOV_FED_B32</h4>
    1174 <p>Opcode VOP2: 9 (0x9)<br />
     1230<p>Opcode VOP1: 9 (0x9)<br />
    11751231Opcode VOP3A: 393 (0x189) for GCN 1.0/1.1; 329 (0x149) for GCN 1.2<br />
    11761232Syntax: V_MOV_FED_B32 VDST, SRC0<br />
    … …  
    11781234(???).</p>
    11791235<h4>V_MOV_B32</h4>
    1180 <p>Opcode VOP2: 1 (0x1)<br />
     1236<p>Opcode VOP1: 1 (0x1)<br />
    11811237Opcode VOP3A: 385 (0x181) for GCN 1.0/1.1; 321 (0x141) for GCN 1.2<br />
    11821238Syntax: V_MOV_B32 VDST, SRC0<br />
    … …  
    11851241<code>VDST = SRC0</code></p>
    11861242<h4>V_NOP</h4>
    1187 <p>Opcode VOP2: 0 (0x0)<br />
     1243<p>Opcode VOP1: 0 (0x0)<br />
    11881244Opcode VOP3A: 384 (0x180) for GCN 1.0/1.1; 320 (0x140) for GCN 1.2<br />
    11891245Syntax: V_NOP<br />
    11901246Description: Do nothing.</p>
    11911247<h4>V_READFIRSTLANE_B32</h4>
    1192 <p>Opcode VOP2: 2 (0x2)<br />
     1248<p>Opcode VOP1: 2 (0x2)<br />
    11931249Opcode VOP3A: 386 (0x182) for GCN 1.0/1.1; 322 (0x142) for GCN 1.2<br />
    11941250Syntax: V_READFIRSTLANE_B32 SDST, VSRC0<br />