| 989 | <p>Opcode (VOP3B): 365 (0x16d) for GCN 1.0/1.1; 480 (0x1e0) for GCN 1.2<br /> |
| 990 | Syntax: V_DIV_SCALE_F32 VDST, SDST(2), SRC0, SRC1, SRC2<br /> |
| 991 | Description: Special case divide preop and flags. SRC0 is quotient, SRC1 is denominator, |
| 992 | SRC2 is nominator. All input values are floating point values. SRC0 must be equal SRC1 |
| 993 | or SRC2 (register can be different, only values must be equal). If input different than |
| 994 | SRC0 is greater or equal than T2=POW(2.0, 96+EXP0), (EXP0 is exponent part (base 2) |
| 995 | of SRC0), then instruction multiply SRC0 by POW(2.0, 64), and store that value to VDST, |
| 996 | and set flag in bit for current lane in SDST. Otherwise store SRC0 to VDST and clear flag.<br /> |
| 997 | Operation:<br /> |
| 998 | <code>FLOAT SF0 = ASFLOAT(SRC0) |
| 999 | FLOAT SF1 = ASFLOAT(SRC1) |
| 1000 | FLOAT SF2 = ASFLOAT(SRC2) |
| 1001 | FLOAT S12 = (SRC0!=SRC1) ? SF1 : SF2 |
| 1002 | if (S12 >= POW(2.0, 96+FREXP(SF0)-1) |
| 1003 | { |
| 1004 | VDST = SF0 * POW2(2.0, 64) |
| 1005 | UINT64 MASK = (1ULL<<LANEID) |
| 1006 | SDST = (SDST & ~MASK) | MASK |
| 1007 | } |
| 1008 | else |
| 1009 | { |
| 1010 | VDST = SRC0 |
| 1011 | SDST = (SDST & ~MASK) |
| 1012 | }</code></p> |
| 1014 | <p>Opcode (VOP3B): 366 (0x16e) for GCN 1.0/1.1; 481 (0x1e1) for GCN 1.2<br /> |
| 1015 | Syntax: V_DIV_SCALE_F64 VDST(2), SDST(2), SRC0(2), SRC1(2), SRC2(2)<br /> |
| 1016 | Description: Special case divide preop and flags. SRC0 is quotient, SRC1 is denominator, |
| 1017 | SRC2 is nominator. All input values are double floating point values. |
| 1018 | SRC0 must be equal SRC1 or SRC2 (register can be different, only values must be equal). |
| 1019 | If input different than SRC0 is greater or equal than T2=POW(2.0, 768+EXP0), |
| 1020 | (EXP0 is exponent part (base 2) of SRC0), then instruction multiply SRC0 by POW(2.0, 128), |
| 1021 | and store that value to VDST, and set flag in bit for current lane in SDST. |
| 1022 | Otherwise store SRC0 to VDST and clear flag.<br /> |
| 1023 | Operation:<br /> |
| 1024 | <code>DOUBLE SD0 = ASDOUBLE(SRC0) |
| 1025 | DOUBLE SD1 = ASDOUBLE(SRC1) |
| 1026 | DOUBLE SD2 = ASDOUBLE(SRC2) |
| 1027 | DOUBLE S12 = (SRC0!=SRC1) ? SD1 : SD2 |
| 1028 | UINT64 MASK = (1ULL<<LANEID) |
| 1029 | if (S12 >= POW(2.0, 768+FREXP(SD0)-1) |
| 1030 | { |
| 1031 | VDST = SD0 * POW2(2.0, 128) |
| 1032 | SDST = (SDST & ~MASK) | MASK |
| 1033 | } |
| 1034 | else |
| 1035 | { |
| 1036 | VDST = SRC0 |
| 1037 | SDST = (SDST & ~MASK) |
| 1038 | }</code></p> |