Changes between Version 11 and Version 12 of GcnInstrsVop3
- Timestamp:
- 12/10/15 23:00:19 (8 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
-
GcnInstrsVop3
v11 v12 991 991 Description: Special case divide preop and flags. SRC0 is quotient, SRC1 is denominator, 992 992 SRC2 is nominator. All input values are floating point values. SRC0 must be equal SRC1 993 or SRC2 (register can be different, only values must be equal). If input different than 994 SRC0 is greater or equal than T2=POW(2.0, 96+EXP0), (EXP0 is exponent part (base 2) 995 of SRC0), then instruction multiply SRC0 by POW(2.0, 64), and store that value to VDST, 996 and set flag in bit for current lane in SDST. Otherwise store SRC0 to VDST and clear flag.<br /> 993 or SRC2 (register can be different, only values must be equal). If absolute value of 994 the input different than SRC0 is greater or equal than T2=POW(2.0, 96+EXP0) 995 (EXP0 is exponent part (base 2) of SRC0) or this value is NaN, 996 then instruction multiply SRC0 by POW(2.0, 64), 997 and store that value to VDST, and set flag in bit for current lane in SDST. 998 If SRC0 is NaN or infinity then store SRC0 to VDST and set flag. 999 Otherwise store SRC0 to VDST and clear flag.<br /> 997 1000 Operation:<br /> 998 1001 <code>FLOAT SF0 = ASFLOAT(SRC0) … … 1000 1003 FLOAT SF2 = ASFLOAT(SRC2) 1001 1004 FLOAT S12 = (SRC0!=SRC1) ? SF1 : SF2 1002 if (S12 >= POW(2.0, 96+FREXP(SF0)-1) 1005 if (ISNAN(SF0) || ABS(SF0) == INF) 1006 { 1007 VDST = SRC0 1008 SDST = (SDST & ~MASK) | MASK 1009 } 1010 else if (ABS(S12) >= ABS(POW(2.0, 96+FREXP(SF0)-1) || ISNAN(S12)) 1003 1011 { 1004 1012 VDST = SF0 * POW2(2.0, 64) … … 1017 1025 SRC2 is nominator. All input values are double floating point values. 1018 1026 SRC0 must be equal SRC1 or SRC2 (register can be different, only values must be equal). 1019 If input different than SRC0 is greater or equal than T2=POW(2.0, 768+EXP0), 1020 (EXP0 is exponent part (base 2) of SRC0), then instruction multiply SRC0 by POW(2.0, 128), 1027 If absolute value of the input different than SRC0 is greater or equal than 1028 T2=POW(2.0, 768+EXP0) (EXP0 is exponent part (base 2) of SRC0) or this value is NaN, 1029 then instruction multiply SRC0 by POW(2.0, 128), 1021 1030 and store that value to VDST, and set flag in bit for current lane in SDST. 1031 If SRC0 is NaN or infinity then store SRC0 to VDST and set flag. 1022 1032 Otherwise store SRC0 to VDST and clear flag.<br /> 1023 1033 Operation:<br /> … … 1027 1037 DOUBLE S12 = (SRC0!=SRC1) ? SD1 : SD2 1028 1038 UINT64 MASK = (1ULL<<LANEID) 1029 if (S12 >= POW(2.0, 768+FREXP(SD0)-1) 1039 if (ISNAN(SD0) || ABS(SD0) == INF) 1040 { 1041 VDST = SRC0 1042 SDST = (SDST & ~MASK) | MASK 1043 } 1044 else if (ABS(S12) >= ABS(POW(2.0, 768+FREXP(SD0)-1) || ISNAN(S12)) 1030 1045 { 1031 1046 VDST = SD0 * POW2(2.0, 128)