Changes between Version 7 and Version 8 of GcnInstrsVop3


Ignore:
Timestamp:
12/07/15 23:00:19 (8 years ago)
Author:
trac
Comment:

--

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  • GcnInstrsVop3

    v7 v8  
    795795<h3>Instruction set</h3>
    796796<p>Alphabetically sorted instruction list:</p>
     797<h4>V_ADD_F64</h4>
     798<p>Opcode: 356 (0x164) for GCN 1.0/1.1; 640 (0x280) for GCN 1.2<br />
     799Syntax: V_ADD_F64 VDST(2), SRC0(2), SRC1(2)<br />
     800Description: Add two double FP value from SRC0 and SRC1 and store result to VDST.<br />
     801Operation:<br />
     802<code>VDST = ASDOUBLE(SRC0) + ASDOUBLE(SRC1)</code></p>
    797803<h4>V_ALIGNBIT_B32</h4>
    798804<p>Opcode: 334 (0x14e) for GCN 1.0/1.1; 462 (0x1ce) for GCN 1.2<br />
     
    809815Operation:<br />
    810816<code>VDST = (((UINT64)SRC0)&lt;&lt;32) | SRC1) &gt;&gt; ((SRC2&amp;3)*8)</code></p>
     817<h4>V_ASHR_I64</h4>
     818<p>Opcode: 355 (0x163) for GCN 1.0/1.1<br />
     819Syntax: V_ASHR_I32 VDST(2), SRC0(2), SRC1<br />
     820Description: Arithmetic shift right SRC0 by (SRC1&amp;63) bits and store result into VDST.<br />
     821Operation:<br />
     822<code>VDST = (INT64)SRC0 &gt;&gt; (SRC1&amp;63)</code></p>
    811823<h4>V_BFE_I32</h4>
    812824<p>Opcode: 329 (0x149) for GCN 1.0/1.1; 457 (0x1c9) for GCN 1.2<br />
     
    924936    VAL8 = (UINT8)MAX(MIN(f, 255.0), 0.0)
    925937VDST = (SRC2&amp;~mask) | (((UINT32)VAL8) &lt;&lt; shift)</code></p>
     938<h4>V_DIV_FIXUP_F32</h4>
     939<p>Opcode: 351 (0x15f) for GCN 1.0/1.1; 478 (0x1de) for GCN 1.2<br />
     940Syntax: V_DIV_FIXUP_F32 VDST, SRC0, SRC1, SRC2<br />
     941Description: Handle all exceptions requires for single floating point division.
     942SRC0 is quotient, SRC1 is denominator, SRC2 is nominator. Correct result stored to VDST.<br />
     943Operation:<br />
     944<code>FLOAT SF0 = ASFLOAT(SRC0)
     945FLOAT SF1 = ASFLOAT(SRC1)
     946FLOAT SF2 = ASFLOAT(SRC2)
     947if (ISNAN(SF1) &amp;&amp; !ISNAN(SF2))
     948    VDST = QUIETNAN(SF1)
     949else if (ISNAN(SF2))
     950    VDST = QUIETNAN(SF2)
     951else if (SF1 == 0.0 &amp;&amp; SF2 == 0.0)
     952    VDST = NAN
     953else if (ABS(SF1)==INF &amp;&amp; ABS(SF2)==INF)
     954    VDST = -NAN
     955else if (SF1 == 0.0)
     956    VDST = INF*SIGN(SF1)*SIGN(SF2)
     957else if (ABS(SF1) == INF)
     958    VDST = SIGN(SF1)*SIGN(SF2) &gt;=0 ? 0.0 : -0.0
     959else if (ISNAN(SF0))
     960    VDST = SIGN(SF1)*SIGN(SF2)*INF
     961else
     962    VDST = SF0</code></p>
     963<h4>V_DIV_FIXUP_F64</h4>
     964<p>Opcode: 352 (0x160) for GCN 1.0/1.1; 479 (0x1df) for GCN 1.2<br />
     965Syntax: V_DIV_FIXUP_F64 VDST(2), SRC0(2), SRC1(2), SRC2(2)<br />
     966Description: Handle all exceptions requires for double floating point division.
     967SRC0 is quotient, SRC1 is denominator, SRC2 is nominator. Correct result stored to VDST.<br />
     968Operation:<br />
     969<code>DOUBLE SF0 = ASDOUBLE(SRC0)
     970DOUBLE SF1 = ASDOUBLE(SRC1)
     971DOUBLE SF2 = ASDOUBLE(SRC2)
     972if (ISNAN(SF1) &amp;&amp; !ISNAN(SF2))
     973    VDST = QUIETNAN(SF1)
     974else if (ISNAN(SF2))
     975    VDST = QUIETNAN(SF2)
     976else if (SF1 == 0.0 &amp;&amp; SF2 == 0.0)
     977    VDST = NAN
     978else if (ABS(SF1)==INF &amp;&amp; ABS(SF2)==INF)
     979    VDST = -NAN
     980else if (SF1 == 0.0)
     981    VDST = INF*SIGN(SF1)*SIGN(SF2)
     982else if (ABS(SF1) == INF)
     983    VDST = SIGN(SF1)*SIGN(SF2) &gt;=0 ? 0.0 : -0.0
     984else if (ISNAN(SF0))
     985    VDST = SIGN(SF1)*SIGN(SF2)*INF
     986else
     987    VDST = SF0</code></p>
    926988<h4>V_FMA_F32</h4>
    927989<p>Opcode: 331 (0x14b) for GCN 1.0/1.1; 459 (0x1cb) for GCN 1.2<br />
     
    9401002<code>// SRC0*SRC1+SRC2
    9411003VDST = FMA(ASDOUBLE(SRC0), ASDOUBLE(SRC1), ASDOUBLE(SRC2))</code></p>
     1004<h4>V_LDEXP_F64</h4>
     1005<p>Opcode: 360 (0x168) for GCN 1.0/1.1; 644 (0x284) for GCN 1.2<br />
     1006Syntax: V_LDEXP_F64 VDST(2), SRC0(2), SRC1<br />
     1007Description: Do ldexp operation on SRC0 and SRC1 (multiply SRC0 by 2**(SRC1)).
     1008SRC1 is signed integer, SRC0 is double floating point value.<br />
     1009Operation:<br />
     1010<code>VDST = ASDOUBLE(SRC0) * POW(2.0, (INT32)SRC1)</code></p>
    9421011<h4>V_LERP_U8</h4>
    9431012<p>Opcode: 333 (0x14d) for GCN 1.0/1.1; 461 (0x1cd) for GCN 1.2<br />
     
    9541023    VDST = (VDST &amp; ~(255U&lt;&lt;(i*8))) | (((S0+S1+S2) &gt;&gt; 1) &lt;&lt; (i*8))
    9551024}</code></p>
     1025<h4>V_LSHL_B64</h4>
     1026<p>Opcode: 353 (0x161) for GCN 1.0/1.1<br />
     1027Syntax: V_LSHL_B32 VDST(2), SRC0(2), SRC1<br />
     1028Description: Shift left SRC0 by (SRC1&amp;63) bits and store result into VDST.<br />
     1029Operation:<br />
     1030<code>VDST = SRC0 &lt;&lt; (SRC1&amp;63)</code></p>
     1031<h4>V_LSHR_B64</h4>
     1032<p>Opcode: 354 (0x162) for GCN 1.0/1.1<br />
     1033Syntax: V_LSHR_B32 VDST(2), SRC0(2), SRC1<br />
     1034Description: Shift right SRC0 by (SRC1&amp;63) bits and store result into VDST.<br />
     1035Operation:<br />
     1036<code>VDST = SRC0 &gt;&gt; (SRC1&amp;63)</code></p>
    9561037<h4>V_MAD_F32</h4>
    9571038<p>Opcode: 321 (0x141) for GCN 1.0/1.1; 449 (0x1c1) for GCN 1.2<br />
     
    9861067Operation:<br />
    9871068<code>VDST = (UINT32)(SRC0&amp;0xffffff) * (UINT32)(SRC1&amp;0xffffff) + SRC2</code></p>
     1069<h4>V_MAX_F64</h4>
     1070<p>Opcode: 359 (0x167) for GCN 1.0/1.1; 643 (0x283) for GCN 1.2<br />
     1071Syntax: V_MAX_F64 VDST(2), SRC0(2), SRC1(2)<br />
     1072Description: Choose largest double FP value from SRC0 and SRC1, and store result to VDST.<br />
     1073Operation:<br />
     1074<code>VDST = MAX((ASDOUBLE(SRC0), ASDOUBLE(SRC1))</code></p>
    9881075<h4>V_MAX3_F32</h4>
    9891076<p>Opcode: 340 (0x154) for GCN 1.0/1.1; 467 (0x1d3) for GCN 1.2<br />
     
    10711158else
    10721159    VDST = SRC0</code></p>
     1160<h4>V_MIN_F64</h4>
     1161<p>Opcode: 358 (0x166) for GCN 1.0/1.1; 642 (0x282) for GCN 1.2<br />
     1162Syntax: V_MIN_F64 VDST(2), SRC0(2), SRC1(2)<br />
     1163Description: Choose smallest double FP value from SRC0 and SRC1, and store result to VDST.<br />
     1164Operation:<br />
     1165<code>VDST = MIN((ASDOUBLE(SRC0), ASDOUBLE(SRC1))</code></p>
    10731166<h4>V_MIN3_F32</h4>
    10741167<p>Opcode: 337 (0x151) for GCN 1.0/1.1; 464 (0x1d0) for GCN 1.2<br />
     
    11091202else
    11101203    VDST = MIN(SRC1, SRC0)</code></p>
     1204<h4>V_MUL_F64</h4>
     1205<p>Opcode: 357 (0x165) for GCN 1.0/1.1; 641 (0x281) for GCN 1.2<br />
     1206Syntax: V_MUL_F64 VDST(2), SRC0(2), SRC1(2)<br />
     1207Description: Multiply two double FP values from SRC0 and SRC1 and store result to VDST.<br />
     1208Operation:<br />
     1209<code>VDST = ASDOUBLE(SRC0) * ASDOUBLE(SRC1)</code></p>
    11111210<h4>V_MULLIT_F32</h4>
    11121211<p>Opcode: 336 (0x150) for GCN 1.0/1.1<br />