Changes between Version 7 and Version 8 of GcnInstrsVop3
- Timestamp:
- 12/07/15 23:00:19 (8 years ago)
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GcnInstrsVop3
v7 v8 795 795 <h3>Instruction set</h3> 796 796 <p>Alphabetically sorted instruction list:</p> 797 <h4>V_ADD_F64</h4> 798 <p>Opcode: 356 (0x164) for GCN 1.0/1.1; 640 (0x280) for GCN 1.2<br /> 799 Syntax: V_ADD_F64 VDST(2), SRC0(2), SRC1(2)<br /> 800 Description: Add two double FP value from SRC0 and SRC1 and store result to VDST.<br /> 801 Operation:<br /> 802 <code>VDST = ASDOUBLE(SRC0) + ASDOUBLE(SRC1)</code></p> 797 803 <h4>V_ALIGNBIT_B32</h4> 798 804 <p>Opcode: 334 (0x14e) for GCN 1.0/1.1; 462 (0x1ce) for GCN 1.2<br /> … … 809 815 Operation:<br /> 810 816 <code>VDST = (((UINT64)SRC0)<<32) | SRC1) >> ((SRC2&3)*8)</code></p> 817 <h4>V_ASHR_I64</h4> 818 <p>Opcode: 355 (0x163) for GCN 1.0/1.1<br /> 819 Syntax: V_ASHR_I32 VDST(2), SRC0(2), SRC1<br /> 820 Description: Arithmetic shift right SRC0 by (SRC1&63) bits and store result into VDST.<br /> 821 Operation:<br /> 822 <code>VDST = (INT64)SRC0 >> (SRC1&63)</code></p> 811 823 <h4>V_BFE_I32</h4> 812 824 <p>Opcode: 329 (0x149) for GCN 1.0/1.1; 457 (0x1c9) for GCN 1.2<br /> … … 924 936 VAL8 = (UINT8)MAX(MIN(f, 255.0), 0.0) 925 937 VDST = (SRC2&~mask) | (((UINT32)VAL8) << shift)</code></p> 938 <h4>V_DIV_FIXUP_F32</h4> 939 <p>Opcode: 351 (0x15f) for GCN 1.0/1.1; 478 (0x1de) for GCN 1.2<br /> 940 Syntax: V_DIV_FIXUP_F32 VDST, SRC0, SRC1, SRC2<br /> 941 Description: Handle all exceptions requires for single floating point division. 942 SRC0 is quotient, SRC1 is denominator, SRC2 is nominator. Correct result stored to VDST.<br /> 943 Operation:<br /> 944 <code>FLOAT SF0 = ASFLOAT(SRC0) 945 FLOAT SF1 = ASFLOAT(SRC1) 946 FLOAT SF2 = ASFLOAT(SRC2) 947 if (ISNAN(SF1) && !ISNAN(SF2)) 948 VDST = QUIETNAN(SF1) 949 else if (ISNAN(SF2)) 950 VDST = QUIETNAN(SF2) 951 else if (SF1 == 0.0 && SF2 == 0.0) 952 VDST = NAN 953 else if (ABS(SF1)==INF && ABS(SF2)==INF) 954 VDST = -NAN 955 else if (SF1 == 0.0) 956 VDST = INF*SIGN(SF1)*SIGN(SF2) 957 else if (ABS(SF1) == INF) 958 VDST = SIGN(SF1)*SIGN(SF2) >=0 ? 0.0 : -0.0 959 else if (ISNAN(SF0)) 960 VDST = SIGN(SF1)*SIGN(SF2)*INF 961 else 962 VDST = SF0</code></p> 963 <h4>V_DIV_FIXUP_F64</h4> 964 <p>Opcode: 352 (0x160) for GCN 1.0/1.1; 479 (0x1df) for GCN 1.2<br /> 965 Syntax: V_DIV_FIXUP_F64 VDST(2), SRC0(2), SRC1(2), SRC2(2)<br /> 966 Description: Handle all exceptions requires for double floating point division. 967 SRC0 is quotient, SRC1 is denominator, SRC2 is nominator. Correct result stored to VDST.<br /> 968 Operation:<br /> 969 <code>DOUBLE SF0 = ASDOUBLE(SRC0) 970 DOUBLE SF1 = ASDOUBLE(SRC1) 971 DOUBLE SF2 = ASDOUBLE(SRC2) 972 if (ISNAN(SF1) && !ISNAN(SF2)) 973 VDST = QUIETNAN(SF1) 974 else if (ISNAN(SF2)) 975 VDST = QUIETNAN(SF2) 976 else if (SF1 == 0.0 && SF2 == 0.0) 977 VDST = NAN 978 else if (ABS(SF1)==INF && ABS(SF2)==INF) 979 VDST = -NAN 980 else if (SF1 == 0.0) 981 VDST = INF*SIGN(SF1)*SIGN(SF2) 982 else if (ABS(SF1) == INF) 983 VDST = SIGN(SF1)*SIGN(SF2) >=0 ? 0.0 : -0.0 984 else if (ISNAN(SF0)) 985 VDST = SIGN(SF1)*SIGN(SF2)*INF 986 else 987 VDST = SF0</code></p> 926 988 <h4>V_FMA_F32</h4> 927 989 <p>Opcode: 331 (0x14b) for GCN 1.0/1.1; 459 (0x1cb) for GCN 1.2<br /> … … 940 1002 <code>// SRC0*SRC1+SRC2 941 1003 VDST = FMA(ASDOUBLE(SRC0), ASDOUBLE(SRC1), ASDOUBLE(SRC2))</code></p> 1004 <h4>V_LDEXP_F64</h4> 1005 <p>Opcode: 360 (0x168) for GCN 1.0/1.1; 644 (0x284) for GCN 1.2<br /> 1006 Syntax: V_LDEXP_F64 VDST(2), SRC0(2), SRC1<br /> 1007 Description: Do ldexp operation on SRC0 and SRC1 (multiply SRC0 by 2**(SRC1)). 1008 SRC1 is signed integer, SRC0 is double floating point value.<br /> 1009 Operation:<br /> 1010 <code>VDST = ASDOUBLE(SRC0) * POW(2.0, (INT32)SRC1)</code></p> 942 1011 <h4>V_LERP_U8</h4> 943 1012 <p>Opcode: 333 (0x14d) for GCN 1.0/1.1; 461 (0x1cd) for GCN 1.2<br /> … … 954 1023 VDST = (VDST & ~(255U<<(i*8))) | (((S0+S1+S2) >> 1) << (i*8)) 955 1024 }</code></p> 1025 <h4>V_LSHL_B64</h4> 1026 <p>Opcode: 353 (0x161) for GCN 1.0/1.1<br /> 1027 Syntax: V_LSHL_B32 VDST(2), SRC0(2), SRC1<br /> 1028 Description: Shift left SRC0 by (SRC1&63) bits and store result into VDST.<br /> 1029 Operation:<br /> 1030 <code>VDST = SRC0 << (SRC1&63)</code></p> 1031 <h4>V_LSHR_B64</h4> 1032 <p>Opcode: 354 (0x162) for GCN 1.0/1.1<br /> 1033 Syntax: V_LSHR_B32 VDST(2), SRC0(2), SRC1<br /> 1034 Description: Shift right SRC0 by (SRC1&63) bits and store result into VDST.<br /> 1035 Operation:<br /> 1036 <code>VDST = SRC0 >> (SRC1&63)</code></p> 956 1037 <h4>V_MAD_F32</h4> 957 1038 <p>Opcode: 321 (0x141) for GCN 1.0/1.1; 449 (0x1c1) for GCN 1.2<br /> … … 986 1067 Operation:<br /> 987 1068 <code>VDST = (UINT32)(SRC0&0xffffff) * (UINT32)(SRC1&0xffffff) + SRC2</code></p> 1069 <h4>V_MAX_F64</h4> 1070 <p>Opcode: 359 (0x167) for GCN 1.0/1.1; 643 (0x283) for GCN 1.2<br /> 1071 Syntax: V_MAX_F64 VDST(2), SRC0(2), SRC1(2)<br /> 1072 Description: Choose largest double FP value from SRC0 and SRC1, and store result to VDST.<br /> 1073 Operation:<br /> 1074 <code>VDST = MAX((ASDOUBLE(SRC0), ASDOUBLE(SRC1))</code></p> 988 1075 <h4>V_MAX3_F32</h4> 989 1076 <p>Opcode: 340 (0x154) for GCN 1.0/1.1; 467 (0x1d3) for GCN 1.2<br /> … … 1071 1158 else 1072 1159 VDST = SRC0</code></p> 1160 <h4>V_MIN_F64</h4> 1161 <p>Opcode: 358 (0x166) for GCN 1.0/1.1; 642 (0x282) for GCN 1.2<br /> 1162 Syntax: V_MIN_F64 VDST(2), SRC0(2), SRC1(2)<br /> 1163 Description: Choose smallest double FP value from SRC0 and SRC1, and store result to VDST.<br /> 1164 Operation:<br /> 1165 <code>VDST = MIN((ASDOUBLE(SRC0), ASDOUBLE(SRC1))</code></p> 1073 1166 <h4>V_MIN3_F32</h4> 1074 1167 <p>Opcode: 337 (0x151) for GCN 1.0/1.1; 464 (0x1d0) for GCN 1.2<br /> … … 1109 1202 else 1110 1203 VDST = MIN(SRC1, SRC0)</code></p> 1204 <h4>V_MUL_F64</h4> 1205 <p>Opcode: 357 (0x165) for GCN 1.0/1.1; 641 (0x281) for GCN 1.2<br /> 1206 Syntax: V_MUL_F64 VDST(2), SRC0(2), SRC1(2)<br /> 1207 Description: Multiply two double FP values from SRC0 and SRC1 and store result to VDST.<br /> 1208 Operation:<br /> 1209 <code>VDST = ASDOUBLE(SRC0) * ASDOUBLE(SRC1)</code></p> 1111 1210 <h4>V_MULLIT_F32</h4> 1112 1211 <p>Opcode: 336 (0x150) for GCN 1.0/1.1<br />