Changes between Version 2 and Version 3 of GcnInstrsVop3p
- Timestamp:
- 11/27/17 16:00:36 (6 years ago)
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GcnInstrsVop3p
v2 v3 80 80 <li>OP_SEL:VALUE|[B0,...] - operand lower half selection (0 - lower 16-bits, 1 - bits)</li> 81 81 <li>OP_SEL_HI:VALUE|[B0,...] - operand higher half selection (0 - lower 16-bits, 1 - bits)</li> 82 <li>NEG - negate floating point value from lower part.</li> 83 <li>NEG_HI - negate floating point value from higher part.</li> 82 84 </ul> 83 85 <p>Operand half selection (OP_SEL) take value with bits number depends of number operands. … … 224 226 <h3>Instruction set</h3> 225 227 <p>Alphabetically sorted instruction list:</p> 228 <h4>V_MAD_MIX_F32</h4> 229 <p>Opcode: 32 (0x20)<br /> 230 Syntax: V_MAD_MIX_F32 VDST, SRC0, SRC1, SRC2<br /> 231 Description: Multiply single FP value from SRC0 by single FP value SRC1 and add 232 single FP value from SRC2, and store result to VDST. NEG_HI changes meaning 233 to absolute-value modifier. The OP_SEL_HI controls left-shifting of source operands by 234 16 bits (???).<br /> 235 <code>UINT32 SS0 = OP_SEL_HI&1 ? SRC0<<16 : SRC0 236 UINT32 SS1 = OP_SEL_HI&2 ? SRC1<<16 : SRC1 237 UINT32 SS2 = OP_SEL_HI&4 ? SRC2<<16 : SRC2 238 FLOAT S0 = NEG_HI&1 ? ABS(ASFLOAT(SS0)) : ASFLOAT(SS0) 239 FLOAT S1 = NEG_HI&2 ? ABS(ASFLOAT(SS1)) : ASFLOAT(SS1) 240 FLOAT S2 = NEG_HI&3 ? ABS(ASFLOAT(SS2)) : ASFLOAT(SS2) 241 VDST = S0 * S1 + S2</code></p> 226 242 <h4>V_PK_ADD_F16</h4> 227 243 <p>Opcode: 15 (0xf)<br />