Changes between Version 3 and Version 4 of GcnInstrsVop3p


Ignore:
Timestamp:
11/27/17 19:00:32 (6 years ago)
Author:
trac
Comment:

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Legend:

Unmodified
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  • GcnInstrsVop3p

    v3 v4  
    238238FLOAT S0 = NEG_HI&1 ? ABS(ASFLOAT(SS0)) : ASFLOAT(SS0)
    239239FLOAT S1 = NEG_HI&2 ? ABS(ASFLOAT(SS1)) : ASFLOAT(SS1)
    240 FLOAT S2 = NEG_HI&3 ? ABS(ASFLOAT(SS2)) : ASFLOAT(SS2)
     240FLOAT S2 = NEG_HI&4 ? ABS(ASFLOAT(SS2)) : ASFLOAT(SS2)
    241241VDST = S0 * S1 + S2</code></p>
     242<h4>V_MAD_MIXLO_F16</h4>
     243<p>Opcode: 33 (0x21)<br />
     244Syntax: V_MAD_MIXLO_F16 VDST, SRC0, SRC1, SRC2<br />
     245Description: Multiply half FP value from SRC0 by half FP value SRC1 and add
     246half FP value from SRC2, and store result to lower 16-bit of VDST. NEG_HI changes meaning
     247to absolute-value modifier.<br />
     248<code>HALF S0 = NEG_HI&amp;1 ? ABS(ASHALF(SRC0)) : ASHALF(SRC0)
     249HALF S1 = NEG_HI&amp;2 ? ABS(ASHALF(SRC1)) : ASHALF(SRC1)
     250HALF S2 = NEG_HI&amp;4 ? ABS(ASHALF(SRC2)) : ASHALF(SRC2)
     251VDST = (ASUINT16(S0 * S1 + S2)&amp;0xfff) | (VDST&amp;0xffff0000)</code></p>
     252<h4>V_MAD_MIXHI_F16</h4>
     253<p>Opcode: 34 (0x22)<br />
     254Syntax: V_MAD_MIXHI_F16 VDST, SRC0, SRC1, SRC2<br />
     255Description: Multiply half FP value from SRC0 by half FP value SRC1 and add
     256half FP value from SRC2, and store result to higher 16-bit part of VDST.
     257NEG_HI changes meaning to absolute-value modifier.<br />
     258<code>HALF S0 = NEG_HI&amp;1 ? ABS(ASHALF(SRC0)) : ASHALF(SRC0)
     259HALF S1 = NEG_HI&amp;2 ? ABS(ASHALF(SRC1)) : ASHALF(SRC1)
     260HALF S2 = NEG_HI&amp;4 ? ABS(ASHALF(SRC2)) : ASHALF(SRC2)
     261VDST = (ASUINT16(S0 * S1 + S2)&lt;&lt;16)) | (VDST&amp;0xffff)</code></p>
    242262<h4>V_PK_ADD_F16</h4>
    243263<p>Opcode: 15 (0xf)<br />