| 242 | <h4>V_MAD_MIXLO_F16</h4> |
| 243 | <p>Opcode: 33 (0x21)<br /> |
| 244 | Syntax: V_MAD_MIXLO_F16 VDST, SRC0, SRC1, SRC2<br /> |
| 245 | Description: Multiply half FP value from SRC0 by half FP value SRC1 and add |
| 246 | half FP value from SRC2, and store result to lower 16-bit of VDST. NEG_HI changes meaning |
| 247 | to absolute-value modifier.<br /> |
| 248 | <code>HALF S0 = NEG_HI&1 ? ABS(ASHALF(SRC0)) : ASHALF(SRC0) |
| 249 | HALF S1 = NEG_HI&2 ? ABS(ASHALF(SRC1)) : ASHALF(SRC1) |
| 250 | HALF S2 = NEG_HI&4 ? ABS(ASHALF(SRC2)) : ASHALF(SRC2) |
| 251 | VDST = (ASUINT16(S0 * S1 + S2)&0xfff) | (VDST&0xffff0000)</code></p> |
| 252 | <h4>V_MAD_MIXHI_F16</h4> |
| 253 | <p>Opcode: 34 (0x22)<br /> |
| 254 | Syntax: V_MAD_MIXHI_F16 VDST, SRC0, SRC1, SRC2<br /> |
| 255 | Description: Multiply half FP value from SRC0 by half FP value SRC1 and add |
| 256 | half FP value from SRC2, and store result to higher 16-bit part of VDST. |
| 257 | NEG_HI changes meaning to absolute-value modifier.<br /> |
| 258 | <code>HALF S0 = NEG_HI&1 ? ABS(ASHALF(SRC0)) : ASHALF(SRC0) |
| 259 | HALF S1 = NEG_HI&2 ? ABS(ASHALF(SRC1)) : ASHALF(SRC1) |
| 260 | HALF S2 = NEG_HI&4 ? ABS(ASHALF(SRC2)) : ASHALF(SRC2) |
| 261 | VDST = (ASUINT16(S0 * S1 + S2)<<16)) | (VDST&0xffff)</code></p> |