Changes between Version 14 and Version 15 of GcnMemHandling


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Timestamp:
Dec 29, 2017, 2:00:36 PM (3 weeks ago)
Author:
trac
Comment:

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  • GcnMemHandling

    v14 v15  
    460460For STRIDE!=0 if AINDEX >= NUMRECORDS or OFFSET >= STRIDE when IDXEN or
    461461TID_ENABLE is set, then an address is out of range. Reads are zero and writes are ignored
    462 for an addresses out of range.</p>
     462for addresses out of range.</p>
    463463<p>For 32-bit and wider operations, an address are aligned to 4 bytes.
    464464For 16-bit operations, an address are aligned to 2 bytes.</p>
     
    14851485</table>
    14861486<h3>Image addressing</h3>
    1487 <p>The main addressing rules for images are defined by tiling registers.
     1487<p>The main addressing rules for the images are defined by the tiling registers.
    14881488The TILINGINDEX choose what register control addressing of image. Index 8 (by default)
    1489 choose the linear access. In the most cases images are splitted into tiles which
     1489choose the linear access. In the most cases images are splitted into the tiles which
    14901490organizes image's data in efficient manner for GPU memory subsystem. Unfortunatelly,
    1491 fields of tiling registers and their meanigful are not known (for me).</p>
     1491the fields of the tiling registers and their meanigful are not known (for me).</p>
    14921492<p>The address of image's pixel is stored in VADDR registers. Number of used registers and
    14931493data type depends on the instruction type and image type. Following table describes
     
    16131613<p>About accuracy: Threshold of coordinates for image's sampling are 1/256 of distance
    16141614between pixels.</p>
    1615 <p>The sampling of mipmaps requires normalized coordinates.</p>
     1615<p>The sampling of the mipmaps requires normalized coordinates.</p>
    16161616<h3>Flat addressing</h3>
    16171617<p>By default, FLAT instructions read or write values from main memory.