| 460 | <h3>GPR indexing mode (GCN 1.2)</h3> |
| 461 | <p>The GCN 1.2 introduces the GPR indexing mode that facilitate usage of indexing in VGPR's. |
| 462 | The bit 27 in MODE register indicates whether this mode is enabled. |
| 463 | The M0 register holds index and mode of GPR indexing. If this mode will be enabled |
| 464 | then this index will be added to index of specified VGPR used in vector instruction. |
| 465 | The mode specifies to which operand of vector instruction a GPR index will be added. |
| 466 | If sum of GPR index and VGPR register index beyond last available VGPR register or |
| 467 | this is not a VGPR register (SGPR or other), then operand register will be substituted by |
| 468 | V0 register.</p> |
| 469 | <p>The lowest 8 bits of M0 register holds the GPR index. The 12-15 bits holds GPR indexing mode. |
| 470 | The GPR indexing mode bits table:</p> |
| 471 | <table> |
| 472 | <thead> |
| 473 | <tr> |
| 474 | <th>Bit</th> |
| 475 | <th>Description</th> |
| 476 | </tr> |
| 477 | </thead> |
| 478 | <tbody> |
| 479 | <tr> |
| 480 | <td>0</td> |
| 481 | <td>Apply GPR indexing to VSRC0 operand</td> |
| 482 | </tr> |
| 483 | <tr> |
| 484 | <td>1</td> |
| 485 | <td>Apply GPR indexing to VSRC1 operand</td> |
| 486 | </tr> |
| 487 | <tr> |
| 488 | <td>2</td> |
| 489 | <td>Apply GPR indexing to VSRC2 operand</td> |
| 490 | </tr> |
| 491 | <tr> |
| 492 | <td>3</td> |
| 493 | <td>Apply GPR indexing to VDST operand</td> |
| 494 | </tr> |
| 495 | </tbody> |
| 496 | </table> |