source: CLRX/CLRadeonExtender/trunk/ChangeLog @ 4652

Last change on this file since 4652 was 4649, checked in by matszpk, 9 months ago

CLRadeonExtender: Update change log.

File size: 10.1 KB
2Change Log
4CLRadeonExtender 0.1.8:
6* add chapter about binary formats to CLRX documentation
7* add some informations about compilation under FreeBSD
8* add '.nosectdiffs' to disable new section difference behaviour if new ROCm format choosen
9* small optimization in the AsmScope destructor.
10* add extra info about setting up number of the SGPRs register in documentation
11* fixed OpenCL detection for AMDGPU-PRO
12* add '.enum' pseudo-op to simplify defining enumerations
14* add policy to unify SGPR counting for all binary formats (by default disabled)
15* in documentation fix some some mistakes about building
16* add preliminary support for CPU architectures (untested): SPARC, IA64 and MIPS
17* add new '.dims' syntax for distinguish vector group ids and scalar local ids
18* improve CLZ32/64 for MSVC
19* introduce CTZ32/64
20* while disassemblying determine minimal AMD driver version for GPU device type
21  (better code detection while disassemblying)
22* fixed some types in documentation
23* update list of GPU devices in documentation
24* fix stupid and old bug in ImageMix sample
25* change a GPU device name for VEGA11 to GFX902
26* fixed segfault when attempt to disassemble old Gallium binaries using new Gallium binary format
27* sort the kernels by an offset order by disassemblying
28* better input data checking while disassemblying code
29* add HSALayout mode for AMDCL2 format (similar code layout like in ROCm and Gallium formats)
30* introduce kernel code parts ('.kcode' and '.kcodeend') to AMDCL2
31* check sanity of use LDS in AMD VEGA architecture (can be used only in SCRATCH and GLOBAL)
32* in source code add new types: GPUArchMask, AsmKernelId and AsmSectionId type.
33* allow constant literals in sym regranges
34* fixed symreg ranges checking
35* fixed handling some the symbol names similar to some register names (like exec_masc)
36* add new GPU devices to list (gfx904, gfx905, gfx906 and gfx907)
37* add AMD VEGA 20 instruction set
38* add much stuff to handle register allocation (still it doesn't work and it wasnot finished)
39* add a DTree structure to save memory in storing register allocation structures
40* fixed possible segfault while preparing to write when ASMKERN_INNER is present
42CLRadeonExtender 0.1.7:
44* update AmdCL2ABI chapter
45* fixed kernel arguments sizes in GalliumCompute binary format
46* add new GPU devices gfx902-gfx905
47* update device tables for Amd Crimson drivers
48* small fixes in DynLibrary interface
49* add relocations to GalliumCompute binary format (for scratch buffer symbols)
50* make getXXXDisasmInputFromBinaryXX as public interface
51* speeding up evaluation of simple expressions without symbols
52* add '.for' and '.while' pseudo-ops ('for' and 'while' loops)
53* fixed some grammar/typos in CLRX documentation
54* add GPU device names from ROCm-OpenCL
55* handle new ROCm binary format with YAML metadatas (assembler and disassembler)
56* add few pseudo-ops to ROCm handling
57* add new pseudo-ops to set parameters in ROCm YAML metadata
58* fixes in GalliumCompute binary generator (for conformant with standards)
59* add '.reqd_work_group_size' pseudo-op (equivalent of '.cws')
60* add support for work_group_size_hint and vec_type hint in Amd OpenCL 2.0 binary format
61* some small bug fixes in ROCm disassembler
62* updates in and INSTALL files
63* small sanitizations in DisasmAmd, DisasmAmdCL2 (argument type checking)
64* change behaviour of '.cws' (.reqd_work_group_size) while setting default values
65* add calculation of section differences in an expressions (for ROCm handling)
66* fixed invalid reads (potential segfault) after undefining symbol
67* fixed old stupid bug: resolve symbol value by using new value (or just if undefined then
68  do not resolve symbol) instead old unresolved symbol value later when expression
69  has been evaluated
70* Add GOT table handling in ROCm binary format
71* add new option '--newROCmBinFormat'
72* add untested support for ROCm in CLHelper and VectorAdd sample
73* add support for multiple OpenCL platforms in CLHelper and samples
74* allow te call_convetion to 0xffffffff in AMDHSA config
75* handle special cases with relatives while evaluating binary/logical operators
76* small fixes in CLRX documentation and Unix manuals
77* developing unfinished AsmRegAlloc
78* add a missing access qualifier to images 'read_write' for AMD OpenCL 2.0
80CLRadeonExtender 0.1.6:
82* add support for Mesa3D 17.3.0 (GPU detection)
83* fixed segfaults during disassemblying new Gallium binaries with AMD HSA
84* add ability to supply defined symbols during using the CLHelper
85* fixed CLRXDocs mistakes in GcnSrmdInstrs, GcmSmemInstrs, GcnVopXInstrs chapters.
86* add GCN1.4 (VEGA) instruction's descriptons to CLRXDocs
87* add support for GCN 1.4 (VEGA) to samples
88* fixed encoding/decoding of SMEM instructions with SGPR offset (GCN 1.4)
89* add a missing GCN 1.4 instructions
90* fixed encoding/decoding of OP_SEL (GCN 1.4)
91* fixed encoding/decoding of DS_READ_ADDTID_B32 (GCN 1.4)
92* fixed encoding/decoding of TBUFFER_x_D16/BUFFER_x_D16 instructions for GCN 1.4
93* fixed encoding CLAMP VOP3/VOPC instructions (GCN 1.4)
94* allow to use OMOD, NEG, ABS, CLAMP modifiers in VOP3/VINTRP instructions
95* add new VOP3/VINTRP instruction's descriptions to CLRXDocs
96* update GCN timings chapter in CLRXDocs
98CLRadeonExtender 0.1.5r1:
100* add detection of OpenGL to CMakeLists.txt
101* add more comments in the source code
102* fixed hanging when ROCm code have hundreds or more kernels
103* parameter in modifier can have any value
104* add 'get_version' pseudo-operation
105* add oldModParam mode (old modifier parameter's policy)
106* fixes for ROCm disassembler module
107* fixes for Gallium binary reader (accept new binaries with many kernels)
108* added support for Mesa3D 17.2.x
109* added Mesa3D/Gallium device names for AMD Polaris
110* add new exceptions to code (to distinguish type of exception)
111* fixed position in disassembler code in comments (mainly for Gallium/ROCm)
112* add CLRXCLHelper library to facilitate running assembler code on the OpenCL
113* move some GPU architecture versions tables to GPUId
114* add new testcase GPUId
116CLRadeonExtender 0.1.5:
118* ignore case in an access qualifier name's (Amd and AmdCL2)
119* improve handling a '\()' and '\@'
120* add SDWA and DPP words to set instruction encoding
121* fixing few CLRXDocs typos
122* fixes for AMD RX VEGA (GFX900)
123* disassembler prints an instruction's position in comments
124* update GcnTimings
125* update VectorAdd and ReverseBits for LLVM 4.0 and Mesa3D 17.0.0
126* updates in ImageMix (correct workSize calculating for kernel)
127* small fixes in disassembler
128* disassembler can correctly disassemble GalliumCompute for LLVM 4.0
129* add '--llvmVersion' to clrxdisasm
130* dump AMD HSA configuration for GalliumCompute and AmdCL2 (like in ROCm format)
131* disassembler add '@' to hwreg and sendmsg to make dump compatible with clrxasm
132* add '--HSAConfig' to dump AmdCL2 kernel configuration as AMD HSA config
133* add AMD HSA configuration pseudo-ops to GalliumCompute and AmdCL2 binary formats
134* update device list for Gallium and ROCm binary formats for recognizing device
135* fixed support for LLVM>=3.9 and Mesa3D>=17.0.0 in GalliumCompute
136* add pseudo-op '.default_hsa_features' to AmdCL2, Gallium and ROCm formats
137* update headers in code
138* make error handling more compact in assembler's code
139* fixed '.machine', '.codeversion' handling (do not print obsolete warnings)
140* add pkg-config files to installation
141* remove obsolete warnings in CMakeLists.txt
142* added GFX901 support (RX VEGA with HBCC ?)
143* add Config.h and amdbin/Elf.h headers to Doxygen documentation
144* change lowest device for GCN 1.2 to Iceland in GPUId.
145* add support for Windows developments environments: CygWin and MinGW
146* make detecting of 64-bits more portable in CMakeLists.txt (use compiler to do)
147* checking whether std::call_once is available for non full supported std threads
148* use only C++ compiler to check features (Int128Detect.cpp)
150CLRadeonExtender 0.1.4r1:
152* fixed code operation in SMRD and SMEM instructions
153* fixed parsing symbol register ranges begins from 'exec', 'vcc', 'tma', ...
154* checking end of line at parsing symbol and regvar register ranges
156CLRadeonExtender 0.1.4:
158* add AMD RX VEGA support (GCN 1.4/VEGA)
159* add symbol scopes
160* add support for 32-bit AMD OpenCL 2.0 binaries
161* update GPU device ids to latest drivers
162* add Ellesmere and Baffin support for AMD OpenCL 1.2 binaries
163* add support for LLVM 3.9, LLVM 4.0 and Mesa3D 17.0
164* add new options to clrxasm (--llvmVersion)
165* add GCN 1.2 instruction set documentation
166* add new SMEM instruction (s_buffer_atomics)
167* add GDS segment size to AMD OpenCL 2.0 binaries
168* add code of samples for GCN 1.2
169* add option to use old AMD OpenCL 1.2 binary format into samples
170* add editor's syntax (NotePad++, Kate, Gedit, VIM)
171* minor fixes in GCN assembler
172* add modifier's parametrization
173* add options to control case-sensitiviness in macro names
174* fixed handling AMDOCL names for 32-bit Windows environment
175* add installation rules for AMDGPU-PRO drivers (OpenSUSE and Ubuntu)
176* add new pseudo-ops '.get_64bit', '.get_arch', '.get_format', '.get_gpu'
177* add autodetection for LLVM and Mesa3D version
178* find correct AMDOCL, MesaOCL and llvm-config at runtime
180CLRadeonExtender 0.1.3:
182* ROCm binary format support
183* fixed '.format' pseudo-op
184* fixed resolving variables in some specific cases
185* fixed handling AmdCL2 format for device type later than GCN.1.1
186* small fixes in documentation
187* fixed disassemblying s_waitcnt
188* fixed handling floating point literals in assembler and compatibility mode (bugFP)
189* ARMv8 (AArch64) architecture support
190* Android support
192CLRadeonExtender 0.1.2:
194* AMD OpenCL 2.0 support
195* 64-bit Gallium binary format support
196* support for new closed Linux and Windows drivers
197* new samples
198* documentation for OpenCL 2.0 support (includes ABI)
199* documentation for GCN ISA FLAT encoding
200* lit() specifier to distinguish literal and inline constant
201* alternate macro syntax
202* correct counting registers for automatic configuration
203* fixed handling of conditionals and macro pseudo-ops
204* disassembler can dump configuration in user-friendly form
206CLRadeonExtender 0.1.1:
208* support for Windows
209* register ranges, and symbol's of register ranges
210* GCN ISA documentation
211* fixed AMD Catalyst and Gallium compute binary generator
212* fixed clrxasm
214CLRadeonExtender 0.1:
216* first published version
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