1 | ## GCN ISA VOP2/VOP3 instructions |
---|
2 | |
---|
3 | VOP2 instructions can be encoded in the VOP2 encoding and the VOP3A/VOP3B encoding. |
---|
4 | List of fields for VOP2 encoding: |
---|
5 | |
---|
6 | Bits | Name | Description |
---|
7 | ------|----------|------------------------------ |
---|
8 | 0-8 | SRC0 | First (scalar or vector) source operand |
---|
9 | 9-16 | VSRC1 | Second vector source operand |
---|
10 | 17-24 | VDST | Destination vector operand |
---|
11 | 25-30 | OPCODE | Operation code |
---|
12 | 31 | ENCODING | Encoding type. Must be 0 |
---|
13 | |
---|
14 | Syntax: INSTRUCTION VDST, SRC0, VSRC1 |
---|
15 | |
---|
16 | List of fields for VOP3A/VOP3B encoding (GCN 1.0/1.1): |
---|
17 | |
---|
18 | Bits | Name | Description |
---|
19 | ------|----------|------------------------------ |
---|
20 | 0-7 | VDST | Vector destination operand |
---|
21 | 8-10 | ABS | Absolute modifiers for source operands (VOP3A) |
---|
22 | 8-14 | SDST | Scalar destination operand (VOP3B) |
---|
23 | 11 | CLAMP | CLAMP modifier (VOP3A) |
---|
24 | 15 | CLAMP | CLAMP modifier (VOP3B) |
---|
25 | 17-25 | OPCODE | Operation code |
---|
26 | 26-31 | ENCODING | Encoding type. Must be 0b110100 |
---|
27 | 32-40 | SRC0 | First (scalar or vector) source operand |
---|
28 | 41-49 | SRC1 | Second (scalar or vector) source operand |
---|
29 | 50-58 | SRC2 | Third (scalar or vector) source operand |
---|
30 | 59-60 | OMOD | OMOD modifier. Multiplication modifier |
---|
31 | 61-63 | NEG | Negation modifier for source operands |
---|
32 | |
---|
33 | List of fields for VOP3A/VOP3B encoding (GCN 1.2): |
---|
34 | |
---|
35 | Bits | Name | Description |
---|
36 | ------|----------|------------------------------ |
---|
37 | 0-7 | VDST | Destination vector operand |
---|
38 | 8-10 | ABS | Absolute modifiers for source operands (VOP3A) |
---|
39 | 8-14 | SDST | Scalar destination operand (VOP3B) |
---|
40 | 15 | CLAMP | CLAMP modifier |
---|
41 | 16-25 | OPCODE | Operation code |
---|
42 | 26-31 | ENCODING | Encoding type. Must be 0b110100 |
---|
43 | 32-40 | SRC0 | First (scalar or vector) source operand |
---|
44 | 41-49 | SRC1 | Second (scalar or vector) source operand |
---|
45 | 50-58 | SRC2 | Third (scalar or vector) source operand |
---|
46 | 59-60 | OMOD | OMOD modifier. Multiplication modifier |
---|
47 | 61-63 | NEG | Negation modifier for source operands |
---|
48 | |
---|
49 | Syntax: INSTRUCTION VDST, SRC0, SRC1 [MODIFIERS] |
---|
50 | |
---|
51 | Modifiers: |
---|
52 | |
---|
53 | * CLAMP - clamps destination floating point value in range 0.0-1.0 |
---|
54 | * MUL:2, MUL:4, DIV:2 - OMOD modifiers. Multiply destination floating point value by |
---|
55 | 2.0, 4.0 or 0.5 respectively. Clamping applied after OMOD modifier. |
---|
56 | * -SRC - negate floating point value from source operand. Applied after ABS modifier. |
---|
57 | * ABS(SRC), |SRC| - apply absolute value to source operand |
---|
58 | |
---|
59 | NOTE: OMOD modifier doesn't work if output denormals are allowed |
---|
60 | (5 bit of MODE register for single precision or 7 bit for double precision). |
---|
61 | NOTE: OMOD and CLAMP modifier affects only for instruction that output is |
---|
62 | floating point value. |
---|
63 | NOTE: ABS and negation is applied to source operand for any instruction. |
---|
64 | OMOD: OMOD modifier doesn't work for half precision (FP16) instructions (except V_MAC_F16). |
---|
65 | |
---|
66 | Negation and absolute value can be combined: `-ABS(V0)`. Modifiers CLAMP and |
---|
67 | OMOD (MUL:2, MUL:4 and DIV:2) can be given in random order. |
---|
68 | |
---|
69 | Limitations for operands: |
---|
70 | |
---|
71 | * only one SGPR can be read by instruction. Multiple occurrences of this same |
---|
72 | SGPR is allowed |
---|
73 | * only one literal constant can be used, and only when a SGPR or M0 is not used in |
---|
74 | source operands |
---|
75 | * only SRC0 can holds LDS_DIRECT |
---|
76 | |
---|
77 | Unaligned pairs of SGPRs are allowed in source and destination operands. |
---|
78 | |
---|
79 | VOP2 opcodes (0-63) are reflected in VOP3 in range: 256-319. |
---|
80 | List of the instructions by opcode: |
---|
81 | |
---|
82 | Opcode | Opcode(VOP3)| Mnemonic (GCN1.0/1.1) | Mnemonic (GCN 1.2) |
---|
83 | ------------|-------------|----------------------|------------------------ |
---|
84 | 0 (0x0) | 256 (0x100) | V_CNDMASK_B32 | V_CNDMASK_B32 |
---|
85 | 1 (0x1) | 257 (0x101) | V_READLANE_B32 | V_ADD_F32 |
---|
86 | 2 (0x2) | 258 (0x102) | V_WRITELANE_B32 | V_SUB_F32 |
---|
87 | 3 (0x3) | 259 (0x103) | V_ADD_F32 | V_SUBREV_F32 |
---|
88 | 4 (0x4) | 260 (0x104) | V_SUB_F32 | V_MUL_LEGACY_F32 |
---|
89 | 5 (0x5) | 261 (0x105) | V_SUBREV_F32 | V_MUL_F32 |
---|
90 | 6 (0x6) | 262 (0x106) | V_MAC_LEGACY_F32 | V_MUL_I32_I24 |
---|
91 | 7 (0x7) | 263 (0x107) | V_MUL_LEGACY_F32 | V_MUL_HI_I32_I24 |
---|
92 | 8 (0x8) | 264 (0x108) | V_MUL_F32 | V_MUL_U32_U24 |
---|
93 | 9 (0x9) | 265 (0x109) | V_MUL_I32_I24 | V_MUL_HI_U32_U24 |
---|
94 | 10 (0xa) | 266 (0x10a) | V_MUL_HI_I32_I24 | V_MIN_F32 |
---|
95 | 11 (0xb) | 267 (0x10b) | V_MUL_U32_U24 | V_MAX_F32 |
---|
96 | 12 (0xc) | 268 (0x10c) | V_MUL_HI_U32_U24 | V_MIN_I32 |
---|
97 | 13 (0xd) | 269 (0x10d) | V_MIN_LEGACY_F32 | V_MAX_I32 |
---|
98 | 14 (0xe) | 270 (0x10e) | V_MAX_LEGACY_F32 | V_MIN_U32 |
---|
99 | 15 (0xf) | 271 (0x10f) | V_MIN_F32 | V_MAX_U32 |
---|
100 | 16 (0x10) | 272 (0x110) | V_MAX_F32 | V_LSHRREV_B32 |
---|
101 | 17 (0x11) | 273 (0x111) | V_MIN_I32 | V_ASHRREV_I32 |
---|
102 | 18 (0x12) | 274 (0x112) | V_MAX_I32 | V_LSHLREV_B32 |
---|
103 | 19 (0x13) | 275 (0x113) | V_MIN_U32 | V_AND_B32 |
---|
104 | 20 (0x14) | 276 (0x114) | V_MAX_U32 | V_OR_B32 |
---|
105 | 21 (0x15) | 277 (0x115) | V_LSHR_B32 | V_XOR_B32 |
---|
106 | 22 (0x16) | 278 (0x116) | V_LSHRREV_B32 | V_MAC_F32 |
---|
107 | 23 (0x17) | 279 (0x117) | V_ASHR_I32 | V_MADMK_F32 |
---|
108 | 24 (0x18) | 280 (0x118) | V_ASHRREV_I32 | V_MADAK_F32 |
---|
109 | 25 (0x19) | 281 (0x119) | V_LSHL_B32 | V_ADD_U32 (VOP3B) |
---|
110 | 26 (0x1a) | 282 (0x11a) | V_LSHLREV_B32 | V_SUB_U32 (VOP3B) |
---|
111 | 27 (0x1b) | 283 (0x11b) | V_AND_B32 | V_SUBREV_U32 (VOP3B) |
---|
112 | 28 (0x1c) | 284 (0x11c) | V_OR_B32 | V_ADDC_U32 (VOP3B) |
---|
113 | 29 (0x1d) | 285 (0x11d) | V_XOR_B32 | V_SUBB_U32 (VOP3B) |
---|
114 | 30 (0x1e) | 286 (0x11e) | V_BFM_B32 | V_SUBBREV_U32 (VOP3B) |
---|
115 | 31 (0x1f) | 287 (0x11f) | V_MAC_F32 | V_ADD_F16 |
---|
116 | 32 (0x20) | 288 (0x120) | V_MADMK_F32 | V_SUB_F16 |
---|
117 | 33 (0x21) | 289 (0x121) | V_MADAK_F32 | V_SUBREV_F16 |
---|
118 | 34 (0x22) | 290 (0x122) | V_BCNT_U32_B32 | V_MUL_F16 |
---|
119 | 35 (0x23) | 291 (0x123) | V_MBCNT_LO_U32_B32 | V_MAC_F16 |
---|
120 | 36 (0x24) | 292 (0x124) | V_MBCNT_HI_U32_B32 | V_MADMK_F16 |
---|
121 | 37 (0x25) | 293 (0x125) | V_ADD_I32 (VOP3B) | V_MADAK_F16 |
---|
122 | 38 (0x26) | 294 (0x126) | V_SUB_I32 (VOP3B) | V_ADD_U16 |
---|
123 | 39 (0x27) | 295 (0x127) | V_SUBREV_I32 (VOP3B) | V_SUB_U16 |
---|
124 | 40 (0x28) | 296 (0x128) | V_ADDC_U32 (VOP3B) | V_SUBREV_U16 |
---|
125 | 41 (0x29) | 297 (0x129) | V_SUBB_U32 (VOP3B) | V_MUL_LO_U16 |
---|
126 | 42 (0x2a) | 298 (0x12a) | V_SUBBREV_U32 (VOP3B)| V_LSHLREV_B16 |
---|
127 | 43 (0x2b) | 299 (0x12b) | V_LDEXP_F32 | V_LSHRREV_B16 |
---|
128 | 44 (0x2c) | 300 (0x12c) | V_CVT_PKACCUM_U8_F32 | V_ASHRREV_I16 |
---|
129 | 45 (0x2d) | 301 (0x12d) | V_CVT_PKNORM_I16_F32 | V_MAX_F16 |
---|
130 | 46 (0x2e) | 302 (0x12e) | V_CVT_PKNORM_U16_F32 | V_MIN_F16 |
---|
131 | 47 (0x2f) | 303 (0x12f) | V_CVT_PKRTZ_F16_F32 | V_MAX_U16 |
---|
132 | 48 (0x30) | 304 (0x130) | V_CVT_PK_U16_U32 | V_MAX_I16 |
---|
133 | 49 (0x31) | 305 (0x131) | V_CVT_PK_I16_I32 | V_MIN_U16 |
---|
134 | 50 (0x32) | 306 (0x132) | -- | V_MIN_I16 |
---|
135 | 51 (0x33) | 307 (0x133) | -- | V_LDEXP_F16 |
---|
136 | |
---|
137 | ### Instruction set |
---|
138 | |
---|
139 | Alphabetically sorted instruction list: |
---|
140 | |
---|
141 | #### V_ADD_F16 |
---|
142 | |
---|
143 | Opcode VOP2: 31 (0x1f) for GCN 1.2 |
---|
144 | Opcode VOP3A: 287 (0x11f) for GCN 1.2 |
---|
145 | Syntax: V_ADD_F16 VDST, SRC0, SRC1 |
---|
146 | Description: Add two FP16 values from SRC0 and SRC1 and store result to VDST. |
---|
147 | Operation: |
---|
148 | ``` |
---|
149 | VDST = ASHALF(SRC0) + ASHALF(SRC1) |
---|
150 | ``` |
---|
151 | |
---|
152 | #### V_ADD_F32 |
---|
153 | |
---|
154 | Opcode VOP2: 3 (0x3) for GCN 1.0/1.1; 1 (0x1) for GCN 1.2 |
---|
155 | Opcode VOP3A: 259 (0x103) for GCN 1.0/1.1; 257 (0x101) for GCN 1.2 |
---|
156 | Syntax: V_ADD_F32 VDST, SRC0, SRC1 |
---|
157 | Description: Add two FP values from SRC0 and SRC1 and store result to VDST. |
---|
158 | Operation: |
---|
159 | ``` |
---|
160 | VDST = ASFLOAT(SRC0) + ASFLOAT(SRC1) |
---|
161 | ``` |
---|
162 | |
---|
163 | #### V_ADD_I32, V_ADD_U32 |
---|
164 | |
---|
165 | Opcode VOP2: 37 (0x25) for GCN 1.0/1.1; 25 (0x19) for GCN 1.2 |
---|
166 | Opcode VOP3B: 293 (0x125) for GCN 1.0/1.1; 281 (0x119) for GCN 1.2 |
---|
167 | Syntax VOP2 GCN 1.0/1.1: V_ADD_I32 VDST, VCC, SRC0, SRC1 |
---|
168 | Syntax VOP3B GCN 1.0/1.1: V_ADD_I32 VDST, SDST(2), SRC0, SRC1 |
---|
169 | Syntax VOP2 GCN 1.2: V_ADD_U32 VDST, VCC, SRC0, SRC1 |
---|
170 | Syntax VOP3B GCN 1.2: V_ADD_U32 VDST, SDST(2), SRC0, SRC1 |
---|
171 | Description: Add SRC0 to SRC1 and store result to VDST and store carry flag to |
---|
172 | SDST (or VCC) bit with number that equal to lane id. SDST is 64-bit. |
---|
173 | Bits for inactive threads in SDST are always zeroed. |
---|
174 | Operation: |
---|
175 | ``` |
---|
176 | UINT64 temp = (UINT64)SRC0 + (UINT64)SRC1 |
---|
177 | VDST = temp |
---|
178 | SDST = 0 |
---|
179 | UINT64 mask = (1ULL<<LANEID) |
---|
180 | SDST = (SDST&~mask) | ((temp >> 32) ? mask : 0) |
---|
181 | ``` |
---|
182 | |
---|
183 | #### V_ADD_U16 |
---|
184 | |
---|
185 | Opcode VOP2: 38 (0x26) for GCN 1.2 |
---|
186 | Opcode VOP3A: 294 (0x126) for GCN 1.2 |
---|
187 | Syntax: V_ADD_U16 VDST, SRC0, SRC1 |
---|
188 | Description: Add two 16-bit unsigned values from SRC0 and SRC1 and |
---|
189 | store 16-bit unsigned result to VDST. |
---|
190 | Operation: |
---|
191 | ``` |
---|
192 | VDST = (SRC0 + SRC1) & 0xffff |
---|
193 | ``` |
---|
194 | |
---|
195 | #### V_ADDC_U32 |
---|
196 | |
---|
197 | Opcode VOP2: 40 (0x28) for GCN 1.0/1.1; 28 (0x1c) for GCN 1.2 |
---|
198 | Opcode VOP3B: 296 (0x128) for GCN 1.0/1.1; 284 (0x11c) for GCN 1.2 |
---|
199 | Syntax VOP2 GCN 1.0/1.1: V_ADDC_U32 VDST, VCC, SRC0, SRC1, VCC |
---|
200 | Syntax VOP3B GCN 1.2: V_ADDC_U32 VDST, SDST(2), SRC0, SRC1, SSRC2(2) |
---|
201 | Description: Add SRC0 to SRC1 with carry stored in SSRC2 bit with number that equal lane id, |
---|
202 | and store result to VDST and store carry flag to SDST (or VCC) bit with number |
---|
203 | that equal to lane id. SDST and SSRC2 are 64-bit. |
---|
204 | Bits for inactive threads in SDST are always zeroed. |
---|
205 | Operation: |
---|
206 | ``` |
---|
207 | UINT64 mask = (1ULL<<LANEID) |
---|
208 | UINT8 CC = ((SSRC2&mask) ? 1 : 0) |
---|
209 | UINT64 temp = (UINT64)SRC0 + (UINT64)SRC1 + CC |
---|
210 | SDST = 0 |
---|
211 | VDST = temp |
---|
212 | SDST = (SDST&~mask) | ((temp >> 32) ? mask : 0) |
---|
213 | ``` |
---|
214 | |
---|
215 | #### V_AND_B32 |
---|
216 | |
---|
217 | Opcode: VOP2: 27 (0x1b) for GCN 1.0/1.1; 19 (0x13) for GCN 1.2 |
---|
218 | Opcode: VOP3A: 283 (0x11b) for GCN 1.0/1.1; 275 (0x113) for GCN 1.2 |
---|
219 | Syntax: V_AND_B32 VDST, SRC0, SRC1 |
---|
220 | Description: Do bitwise AND on SRC0 and SRC1, store result to VDST. |
---|
221 | Operation: |
---|
222 | ``` |
---|
223 | VDST = SRC0 & SRC1 |
---|
224 | ``` |
---|
225 | |
---|
226 | #### V_ASHR_I32 |
---|
227 | |
---|
228 | Opcode VOP2: 23 (0x17) for GCN 1.0/1.1 |
---|
229 | Opcode VOP3A: 279 (0x117) for GCN 1.0/1.1 |
---|
230 | Syntax: V_ASHR_I32 VDST, SRC0, SRC1 |
---|
231 | Description: Arithmetic shift right SRC0 by (SRC1&31) bits and store result into VDST. |
---|
232 | Operation: |
---|
233 | ``` |
---|
234 | VDST = (INT32)SRC0 >> (SRC1&31) |
---|
235 | ``` |
---|
236 | |
---|
237 | #### V_ASHRREV_B16 |
---|
238 | |
---|
239 | Opcode VOP2: 44 (0x2c) for GCN 1.2 |
---|
240 | Opcode VOP3A: 300 (0x12c) for GCN 1.2 |
---|
241 | Syntax: V_ASHRREV_B16 VDST, SRC0, SRC1 |
---|
242 | Description: Shift right signed 16-bit value from SRC1 by (SRC0&15) bits and |
---|
243 | store 16-bit signed result into VDST. |
---|
244 | Operation: |
---|
245 | ``` |
---|
246 | VDST = ((INT16)SRC1 >> (SRC0&15)) & 0xffff |
---|
247 | ``` |
---|
248 | |
---|
249 | #### V_ASHRREV_I32 |
---|
250 | |
---|
251 | Opcode VOP2: 24 (0x18) for GCN 1.0/1.1; 16 (0x11) for GCN 1.2 |
---|
252 | Opcode VOP3A: 280 (0x118) for GCN 1.0/1.1; 272 (0x111) for GCN 1.2 |
---|
253 | Syntax: V_ASHRREV_I32 VDST, SRC0, SRC1 |
---|
254 | Description: Arithmetic shift right SRC1 by (SRC0&31) bits and store result into VDST. |
---|
255 | Operation: |
---|
256 | ``` |
---|
257 | VDST = (INT32)SRC1 >> (SRC0&31) |
---|
258 | ``` |
---|
259 | |
---|
260 | #### V_BCNT_U32_B32 |
---|
261 | |
---|
262 | Opcode VOP2: 34 (0x22) for GCN 1.0/1.1 |
---|
263 | Opcode VOP3A: 290 (0x122) for GCN 1.0/1.1 |
---|
264 | Syntax: V_BCNT_U32_B32 VDST, SRC0, SRC1 |
---|
265 | Description: Count bits in SRC0, adds SSRC1, and store result to VDST. |
---|
266 | Operation: |
---|
267 | ``` |
---|
268 | VDST = SRC1 + BITCOUNT(SRC0) |
---|
269 | ``` |
---|
270 | |
---|
271 | #### V_BFM_B32 |
---|
272 | |
---|
273 | Opcode VOP2: 30 (0x1e) for GCN 1.0/1.1 |
---|
274 | Opcode VOP3A: 286 (0x11e) for GCN 1.0/1.1 |
---|
275 | Syntax: V_BFM_B32 VDST, SRC0, SRC1 |
---|
276 | Description: Make 32-bit bitmask from (SRC1 & 31) bit that have length (SRC0 & 31) and |
---|
277 | store it to VDST. |
---|
278 | Operation: |
---|
279 | ``` |
---|
280 | VDST = ((1U << (SRC0&31))-1) << (SRC1&31) |
---|
281 | ``` |
---|
282 | |
---|
283 | #### V_CNDMASK_B32 |
---|
284 | |
---|
285 | Opcode VOP2: 0 (0x0) for GCN 1.0/1.1; 1 (0x0) for GCN 1.2 |
---|
286 | Opcode VOP3A: 256 (0x100) for GCN 1.0/1.1; 256 (0x100) for GCN 1.2 |
---|
287 | Syntax VOP2: V_CNDMASK_B32 VDST, SRC0, SRC1, VCC |
---|
288 | Syntax VOP3A: V_CNDMASK_B32 VDST, SRC0, SRC1, SSRC2(2) |
---|
289 | Description: If bit for current lane of VCC or SDST is set then store SRC1 to VDST, |
---|
290 | otherwise store SRC0 to VDST. |
---|
291 | Operation: |
---|
292 | ``` |
---|
293 | VDST = SSRC2&(1ULL<<LANEID) ? SRC1 : SRC0 |
---|
294 | ``` |
---|
295 | |
---|
296 | #### V_CVT_PK_I16_I32 |
---|
297 | |
---|
298 | Opcode VOP2: 49 (0x31) for GCN 1.0/1.1 |
---|
299 | Opcode VOP3A: 305 (0x131) for GCN 1.0/1.1 |
---|
300 | Syntax: V_CVT_PK_I16_I32 VDST, SRC0, SRC1 |
---|
301 | Description: Convert signed value from SRC0 and SRC1 to signed 16-bit values with |
---|
302 | clamping, and store first value to low 16-bit and second to high 16-bit of the VDST. |
---|
303 | Operation: |
---|
304 | ``` |
---|
305 | INT16 D0 = MAX(MIN((INT32)SRC0, 0x7fff), -0x8000) |
---|
306 | INT16 D1 = MAX(MIN((INT32)SRC1, 0x7fff), -0x8000) |
---|
307 | VDST = D0 | (((UINT32)D1) << 16) |
---|
308 | ``` |
---|
309 | |
---|
310 | #### V_CVT_PK_U16_U32 |
---|
311 | |
---|
312 | Opcode VOP2: 48 (0x30) for GCN 1.0/1.1 |
---|
313 | Opcode VOP3A: 304 (0x130) for GCN 1.0/1.1 |
---|
314 | Syntax: V_CVT_PK_U16_U32 VDST, SRC0, SRC1 |
---|
315 | Description: Convert unsigned value from SRC0 and SRC1 to unsigned 16-bit values with |
---|
316 | clamping, and store first value to low 16-bit and second to high 16-bit of the VDST. |
---|
317 | Operation: |
---|
318 | ``` |
---|
319 | UINT16 D0 = MIN(SRC0, 0xffff) |
---|
320 | UINT16 D1 = MIN(SRC1, 0xffff) |
---|
321 | VDST = D0 | (((UINT32)D1) << 16) |
---|
322 | ``` |
---|
323 | |
---|
324 | #### V_CVT_PKACCUM_U8_F32 |
---|
325 | |
---|
326 | Opcode VOP2: 44 (0x2c) for GCN 1.0/1.1 |
---|
327 | Opcode VOP3A: 300 (0x12c) for GCN 1.0/1.1 |
---|
328 | Syntax: V_CVT_PKACCUM_U8_F32 VDST, SRC0, SRC1 |
---|
329 | Description: Convert floating point value from SRC0 to unsigned byte value with |
---|
330 | rounding mode from MODE register, and store this byte to (SRC1&3)'th byte of VDST. |
---|
331 | Operation: |
---|
332 | ``` |
---|
333 | UINT8 shift = ((SRC1&3) * 8) |
---|
334 | UINT32 mask = 0xff << shift |
---|
335 | FLOAT f = RNDINT(ASFLOAT(SRC0)) |
---|
336 | UINT8 VAL8 = 0 |
---|
337 | if (ISNAN(f)) |
---|
338 | VAL8 = (UINT8)MAX(MIN(f, 255.0), 0.0) |
---|
339 | VDST = (VDST&~mask) | (((UINT32)VAL8) << shift) |
---|
340 | ``` |
---|
341 | |
---|
342 | #### V_CVT_PKNORM_I16_F32 |
---|
343 | |
---|
344 | Opcode VOP2: 45 (0x2d) for GCN 1.0/1.1 |
---|
345 | Opcode VOP3A: 301 (0x12d) for GCN 1.0/1.1 |
---|
346 | Syntax: V_CVT_PKNORM_I16_F32 VDST, SRC0, SRC1 |
---|
347 | Description: Convert normalized FP value from SRC0 and SRC1 to signed 16-bit integers with |
---|
348 | rounding to nearest to even (??), and store first value to low 16-bit and |
---|
349 | second to high 16-bit of the VDST. |
---|
350 | Operation: |
---|
351 | ``` |
---|
352 | INT16 roundNorm(FLOAT S) |
---|
353 | { |
---|
354 | FLOAT f = RNDNEINT(S*32767) |
---|
355 | if (ISNAN(f)) |
---|
356 | return 0 |
---|
357 | return (INT16)MAX(MIN(f, 32767.0), -32767.0) |
---|
358 | } |
---|
359 | VDST = roundNorm(ASFLOAT(SRC0)) | ((UINT32)roundNorm(ASFLOAT(SRC1)) << 16) |
---|
360 | ``` |
---|
361 | |
---|
362 | #### V_CVT_PKNORM_U16_F32 |
---|
363 | |
---|
364 | Opcode VOP2: 46 (0x2e) for GCN 1.0/1.1 |
---|
365 | Opcode VOP3A: 302 (0x12e) for GCN 1.0/1.1 |
---|
366 | Syntax: V_CVT_PKNORM_U16_F32 VDST, SRC0, SRC1 |
---|
367 | Description: Convert normalized FP value from SRC0 and SRC1 to unsigned 16-bit integers with |
---|
368 | rounding to nearest to even (??), and store first value to low 16-bit and |
---|
369 | second to high 16-bit of the VDST. |
---|
370 | Operation: |
---|
371 | ``` |
---|
372 | UINT16 roundNorm(FLOAT S) |
---|
373 | { |
---|
374 | FLOAT f = RNDNEINT(S*65535.0) |
---|
375 | if (ISNAN(f)) |
---|
376 | return 0 |
---|
377 | return (INT16)MAX(MIN(f, 65535.0), 0.0) |
---|
378 | } |
---|
379 | VDST = roundNorm(ASFLOAT(SRC0)) | ((UINT32)roundNorm(ASFLOAT(SRC1)) << 16) |
---|
380 | ``` |
---|
381 | |
---|
382 | #### V_CVT_PKRTZ_F16_F32 |
---|
383 | |
---|
384 | Opcode VOP2: 47 (0x2f) for GCN 1.0/1.1 |
---|
385 | Opcode VOP3A: 303 (0x12f) for GCN 1.0/1.1 |
---|
386 | Syntax: V_CVT_PKRTZ_F16_F32 VDST, SRC0, SRC1 |
---|
387 | Description: Convert normalized FP value from SRC0 and SRC1 to half floating points with |
---|
388 | rounding to zero, and store first value to low 16-bit and |
---|
389 | second to high 16-bit of the VDST. |
---|
390 | Operation: |
---|
391 | ``` |
---|
392 | UINT16 D0 = ASINT16(CVT_HALF_RTZ(ASFLOAT(SRC0))) |
---|
393 | UINT16 D1 = ASINT16(CVT_HALF_RTZ(ASFLOAT(SRC1))) |
---|
394 | VDST = D0 | (((UINT32)D1) << 16) |
---|
395 | ``` |
---|
396 | |
---|
397 | #### V_LDEXP_F16 |
---|
398 | |
---|
399 | Opcode VOP2: 51 (0x33) for GCN 1.2 |
---|
400 | Opcode VOP3A: 307 (0x133) for GCN 1.2 |
---|
401 | Syntax: V_LDEXP_F16 VDST, SRC0, SRC1 |
---|
402 | Description: Do ldexp operation on SRC0 and SRC1 (multiply SRC0 by 2**(SRC1)). |
---|
403 | SRC1 is signed integer, SRC0 is half floating point value. |
---|
404 | Operation: |
---|
405 | ``` |
---|
406 | VDST = ASHALF(SRC0) * POW(2.0, (INT32)SRC1) |
---|
407 | ``` |
---|
408 | |
---|
409 | #### V_LDEXP_F32 |
---|
410 | |
---|
411 | Opcode VOP2: 43 (0x2b) for GCN 1.0/1.1 |
---|
412 | Opcode VOP3A: 299 (0x12b) for GCN 1.0/1.1 |
---|
413 | Syntax: V_LDEXP_F32 VDST, SRC0, SRC1 |
---|
414 | Description: Do ldexp operation on SRC0 and SRC1 (multiply SRC0 by 2**(SRC1)). |
---|
415 | SRC1 is signed integer, SRC0 is floating point value. |
---|
416 | Operation: |
---|
417 | ``` |
---|
418 | VDST = ASFLOAT(SRC0) * POW(2.0, (INT32)SRC1) |
---|
419 | ``` |
---|
420 | |
---|
421 | #### V_LSHL_B32 |
---|
422 | |
---|
423 | Opcode VOP2: 25 (0x19) for GCN 1.0/1.1 |
---|
424 | Opcode VOP3A: 281 (0x119) for GCN 1.0/1.1 |
---|
425 | Syntax: V_LSHL_B32 VDST, SRC0, SRC1 |
---|
426 | Description: Shift left SRC0 by (SRC1&31) bits and store result into VDST. |
---|
427 | Operation: |
---|
428 | ``` |
---|
429 | VDST = SRC0 << (SRC1&31) |
---|
430 | ``` |
---|
431 | |
---|
432 | #### V_LSHLREV_B16 |
---|
433 | |
---|
434 | Opcode VOP2: 42 (0x2a) for GCN 1.2 |
---|
435 | Opcode VOP3A: 298 (0x12a) for GCN 1.2 |
---|
436 | Syntax: V_LSHLREV_B16 VDST, SRC0, SRC1 |
---|
437 | Description: Shift left unsigned 16-bit value from SRC1 by (SRC0&15) bits and |
---|
438 | store 16-bit unsigned result into VDST. |
---|
439 | Operation: |
---|
440 | ``` |
---|
441 | VDST = (SRC1 << (SRC0&15)) & 0xffff |
---|
442 | ``` |
---|
443 | |
---|
444 | #### V_LSHLREV_B32 |
---|
445 | |
---|
446 | Opcode VOP2: 26 (0x1a) for GCN 1.0/1.1; 18 (0x12) for GCN 1.2 |
---|
447 | Opcode VOP3A: 282 (0x11a) for GCN 1.0/1.1; 274 (0x112) for GCN 1.2 |
---|
448 | Syntax: V_LSHLREV_B32 VDST, SRC0, SRC1 |
---|
449 | Description: Shift left SRC1 by (SRC0&31) bits and store result into VDST. |
---|
450 | Operation: |
---|
451 | ``` |
---|
452 | VDST = SRC1 << (SRC0&31) |
---|
453 | ``` |
---|
454 | |
---|
455 | #### V_LSHR_B32 |
---|
456 | |
---|
457 | Opcode VOP2: 21 (0x15) for GCN 1.0/1.1 |
---|
458 | Opcode VOP3A: 277 (0x115) for GCN 1.0/1.1 |
---|
459 | Syntax: V_LSHR_B32 VDST, SRC0, SRC1 |
---|
460 | Description: Shift right SRC0 by (SRC1&31) bits and store result into VDST. |
---|
461 | Operation: |
---|
462 | ``` |
---|
463 | VDST = SRC0 >> (SRC1&31) |
---|
464 | ``` |
---|
465 | |
---|
466 | #### V_LSHRREV_B16 |
---|
467 | |
---|
468 | Opcode VOP2: 43 (0x2b) for GCN 1.2 |
---|
469 | Opcode VOP3A: 299 (0x12b) for GCN 1.2 |
---|
470 | Syntax: V_LSHRREV_B16 VDST, SRC0, SRC1 |
---|
471 | Description: Shift right unsigned 16-bit value from SRC1 by (SRC0&15) bits and |
---|
472 | store 16-bit unsigned result into VDST. |
---|
473 | Operation: |
---|
474 | ``` |
---|
475 | VDST = (SRC1 >> (SRC0&15)) & 0xffff |
---|
476 | ``` |
---|
477 | |
---|
478 | #### V_LSHRREV_B32 |
---|
479 | |
---|
480 | Opcode VOP2: 22 (0x16) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2 |
---|
481 | Opcode VOP3A: 278 (0x116) for GCN 1.0/1.1; 272 (0x110) for GCN 1.2 |
---|
482 | Syntax: V_LSHRREV_B32 VDST, SRC0, SRC1 |
---|
483 | Description: Shift right SRC1 by (SRC0&31) bits and store result into VDST. |
---|
484 | Operation: |
---|
485 | ``` |
---|
486 | VDST = SRC1 >> (SRC0&31) |
---|
487 | ``` |
---|
488 | |
---|
489 | #### V_MAC_F16 |
---|
490 | |
---|
491 | Opcode VOP2: 35 (0x23) for GCN 1.2 |
---|
492 | Opcode VOP3A: 291 (0x123) for GCN 1.2 |
---|
493 | Syntax: V_MAC_F16 VDST, SRC0, SRC1 |
---|
494 | Description: Multiply FP16 value from SRC0 by FP16 value from SRC1 and |
---|
495 | add result to VDST. It applies OMOD modifier to result. |
---|
496 | Operation: |
---|
497 | ``` |
---|
498 | VDST = ASHALF(SRC0) * ASHALF(SRC1) + ASHALF(VDST) |
---|
499 | ``` |
---|
500 | |
---|
501 | #### V_MAC_F32 |
---|
502 | |
---|
503 | Opcode VOP2: 31 (0x1f) for GCN 1.0/1.1; 22 (0x16) for GCN 1.2 |
---|
504 | Opcode VOP3A: 287 (0x11f) for GCN 1.0/1.1; 278 (0x116) for GCN 1.2 |
---|
505 | Syntax: V_MAC_F32 VDST, SRC0, SRC1 |
---|
506 | Description: Multiply FP value from SRC0 by FP value from SRC1 and add result to VDST. |
---|
507 | Operation: |
---|
508 | ``` |
---|
509 | VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1) + ASFLOAT(VDST) |
---|
510 | ``` |
---|
511 | |
---|
512 | #### V_MAC_LEGACY_F32 |
---|
513 | |
---|
514 | Opcode VOP2: 6 (0x6) for GCN 1.0/1.1 |
---|
515 | Opcode VOP3A: 262 (0x106) for GCN 1.0/1.1 |
---|
516 | Syntax: V_MAC_LEGACY_F32 VDST, SRC0, SRC1 |
---|
517 | Description: Multiply FP value from SRC0 by FP value from SRC1 and add result to VDST. |
---|
518 | If one of value is 0.0 then always do not change VDST (do not apply IEEE rules for 0.0*x). |
---|
519 | Operation: |
---|
520 | ``` |
---|
521 | if (ASFLOAT(SRC0)!=0.0 && ASFLOAT(SRC1)!=0.0) |
---|
522 | VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1) + ASFLOAT(VDST) |
---|
523 | ``` |
---|
524 | |
---|
525 | #### V_MADMK_F16 |
---|
526 | |
---|
527 | Opcode: 36 (0x24) for GCN 1.2 |
---|
528 | Opcode: 292 (0x124) for GCN 1.2 |
---|
529 | Syntax: V_MADMK_F16 VDST, SRC0, FLOAT16LIT, SRC1 |
---|
530 | Description: Multiply FP16 value from SRC0 with the constant literal FLOAT16LIT and add |
---|
531 | FP16 value from SRC1; and store result to VDST. Constant literal follows |
---|
532 | after instruction word. Use nearest-even rouding. |
---|
533 | Operation: |
---|
534 | ``` |
---|
535 | VDST = ASHALF(SRC0) * ASHALF(FLOAT16LIT) + ASHALF(SRC1) |
---|
536 | ``` |
---|
537 | |
---|
538 | #### V_MADMK_F32 |
---|
539 | |
---|
540 | Opcode: VOP2: 32 (0x20) for GCN 1.0/1.1; 23 (0x17) for GCN 1.2 |
---|
541 | Opcode: VOP3A: 288 (0x120) for GCN 1.0/1.1; 279 (0x117) for GCN 1.2 |
---|
542 | Syntax: V_MADMK_F32 VDST, SRC0, FLOATLIT, SRC1 |
---|
543 | Description: Multiply FP value from SRC0 with the constant literal FLOATLIT and add |
---|
544 | FP value from SRC1; and store result to VDST. Constant literal follows |
---|
545 | after instruction word. |
---|
546 | Operation: |
---|
547 | ``` |
---|
548 | VDST = ASFLOAT(SRC0) * ASFLOAT(FLOATLIT) + ASFLOAT(SRC1) |
---|
549 | ``` |
---|
550 | |
---|
551 | #### V_MADAK_F16 |
---|
552 | |
---|
553 | Opcode: 37 (0x25) for GCN 1.2 |
---|
554 | Opcode: 293 (0x125) for GCN 1.2 |
---|
555 | Syntax: V_MADAK_F16 VDST, SRC0, SRC1, FLOAT16LIT |
---|
556 | Description: Multiply FP16 value from SRC0 with FP16 value from SRC1 and add |
---|
557 | the constant literal FLOATLIT16; and store result to VDST. Constant literal follows |
---|
558 | after instruction word. |
---|
559 | Operation: |
---|
560 | ``` |
---|
561 | VDST = ASHALF(SRC0) * ASHALF(SRC1) + ASHALF(FLOAT16LIT) |
---|
562 | ``` |
---|
563 | |
---|
564 | #### V_MADAK_F32 |
---|
565 | |
---|
566 | Opcode: VOP2: 33 (0x21) for GCN 1.0/1.1; 24 (0x18) for GCN 1.2 |
---|
567 | Opcode: VOP3A: 289 (0x121) for GCN 1.0/1.1; 280 (0x118) for GCN 1.2 |
---|
568 | Syntax: V_MADAK_F32 VDST, SRC0, SRC1, FLOATLIT |
---|
569 | Description: Multiply FP value from SRC0 with FP value from SRC1 and add |
---|
570 | the constant literal FLOATLIT; and store result to VDST. Constant literal follows |
---|
571 | after instruction word. |
---|
572 | Operation: |
---|
573 | ``` |
---|
574 | VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1) + ASFLOAT(FLOATLIT) |
---|
575 | ``` |
---|
576 | |
---|
577 | #### V_MAX_F16 |
---|
578 | |
---|
579 | Opcode VOP2: 45 (0x2d) for GCN 1.2 |
---|
580 | Opcode VOP3A: 301 (0x12d) for GCN 1.2 |
---|
581 | Syntax: V_MAX_F16 VDST, SRC0, SRC1 |
---|
582 | Description: Choose largest half floating point value from SRC0 and SRC1, |
---|
583 | and store result to VDST. |
---|
584 | Operation: |
---|
585 | ``` |
---|
586 | VDST = MAX(ASFHALF(SRC0), ASFHALF(SRC1)) |
---|
587 | ``` |
---|
588 | |
---|
589 | #### V_MAX_F32 |
---|
590 | |
---|
591 | Opcode VOP2: 16 (0x10) for GCN 1.0/1.1; 11 (0xb) for GCN 1.2 |
---|
592 | Opcode VOP3A: 272 (0x110) for GCN 1.0/1.1; 267 (0x10b) for GCN 1.2 |
---|
593 | Syntax: V_MAX_F32 VDST, SRC0, SRC1 |
---|
594 | Description: Choose largest floating point value from SRC0 and SRC1, |
---|
595 | and store result to VDST. |
---|
596 | Operation: |
---|
597 | ``` |
---|
598 | VDST = MAX(ASFLOAT(SRC0), ASFLOAT(SRC1)) |
---|
599 | ``` |
---|
600 | |
---|
601 | #### V_MAX_I32 |
---|
602 | |
---|
603 | Opcode VOP2: 18 (0x12) for GCN 1.0/1.1; 13 (0xd) for GCN 1.2 |
---|
604 | Opcode VOP3A: 274 (0x112) for GCN 1.0/1.1; 269 (0x10d) for GCN 1.2 |
---|
605 | Syntax: V_MAX_I32 VDST, SRC0, SRC1 |
---|
606 | Description: Choose largest signed value from SRC0 and SRC1, and store result to VDST. |
---|
607 | Operation: |
---|
608 | ``` |
---|
609 | VDST = MAX((INT32)SRC0, (INT32)SRC1) |
---|
610 | ``` |
---|
611 | |
---|
612 | #### V_MAX_LEGACY_F32 |
---|
613 | |
---|
614 | Opcode VOP2: 14 (0xe) for GCN 1.0/1.1 |
---|
615 | Opcode VOP3A: 270 (0x10e) for GCN 1.0/1.1 |
---|
616 | Syntax: V_MAX_LEGACY_F32 VDST, SRC0, SRC1 |
---|
617 | Description: Choose largest floating point value from SRC0 and SRC1, |
---|
618 | and store result to VDST. If SSRC1 is NaN value then store NaN value to VDST |
---|
619 | (legacy rules for handling NaNs). |
---|
620 | Operation: |
---|
621 | ``` |
---|
622 | if (!ISNAN(ASFLOAT(SRC1))) |
---|
623 | VDST = MAX(ASFLOAT(SRC0), ASFLOAT(SRC1)) |
---|
624 | else |
---|
625 | VDST = NaN |
---|
626 | ``` |
---|
627 | |
---|
628 | #### V_MAX_U32 |
---|
629 | |
---|
630 | Opcode VOP2: 20 (0x14) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2 |
---|
631 | Opcode VOP3A: 276 (0x114) for GCN 1.0/1.1; 271 (0x10f) for GCN 1.2 |
---|
632 | Syntax: V_MAX_U32 VDST, SRC0, SRC1 |
---|
633 | Description: Choose largest unsigned value from SRC0 and SRC1, and store result to VDST. |
---|
634 | Operation: |
---|
635 | ``` |
---|
636 | VDST = MAX(SRC0, SRC1) |
---|
637 | ``` |
---|
638 | |
---|
639 | #### V_MBCNT_HI_U32_B32 |
---|
640 | |
---|
641 | Opcode VOP2: 36 (0x24) for GCN 1.0/1.1 |
---|
642 | Opcode VOP3A: 292 (0x124) for GCN 1.0/1.1 |
---|
643 | Syntax: V_MBCNT_HI_U32_B32 VDST, SRC0, SRC1 |
---|
644 | Description: Make mask for all lanes ending at current lane, |
---|
645 | get from that mask higher 32-bits, use it to mask SSRC0, |
---|
646 | count bits in that value, and store result to VDST. |
---|
647 | Operation: |
---|
648 | ``` |
---|
649 | UINT32 MASK = ((1ULL << (LANEID-32)) - 1ULL) & SRC0 |
---|
650 | VDST = SRC1 + BITCOUNT(MASK) |
---|
651 | ``` |
---|
652 | |
---|
653 | #### V_MBCNT_LO_U32_B32 |
---|
654 | |
---|
655 | Opcode VOP2: 35 (0x23) for GCN 1.0/1.1 |
---|
656 | Opcode VOP3A: 291 (0x123) for GCN 1.0/1.1 |
---|
657 | Syntax: V_MBCNT_LO_U32_B32 VDST, SRC0, SRC1 |
---|
658 | Description: Make mask for all lanes ending at current lane, |
---|
659 | get from that mask lower 32-bits, use it to mask SSRC0, |
---|
660 | count bits in that value, and store result to VDST. |
---|
661 | Operation: |
---|
662 | ``` |
---|
663 | UINT32 MASK = ((1ULL << LANEID) - 1ULL) & SRC0 |
---|
664 | VDST = SRC1 + BITCOUNT(MASK) |
---|
665 | ``` |
---|
666 | |
---|
667 | #### V_MIN_F16 |
---|
668 | |
---|
669 | Opcode VOP2: 46 (0x2e) for GCN 1.2 |
---|
670 | Opcode VOP3A: 302 (0x12e) for GCN 1.2 |
---|
671 | Syntax: V_MIN_F16 VDST, SRC0, SRC1 |
---|
672 | Description: Choose smallest half floating point value from SRC0 and SRC1, |
---|
673 | and store result to VDST. |
---|
674 | Operation: |
---|
675 | ``` |
---|
676 | VDST = MIN(ASFHALF(SRC0), ASFHALF(SRC1)) |
---|
677 | ``` |
---|
678 | |
---|
679 | #### V_MIN_F32 |
---|
680 | |
---|
681 | Opcode VOP2: 15 (0xf) for GCN 1.0/1.1; 10 (0xa) for GCN 1.2 |
---|
682 | Opcode VOP3A: 271 (0x10f) for GCN 1.0/1.1; 266 (0x10a) for GCN 1.2 |
---|
683 | Syntax: V_MIN_F32 VDST, SRC0, SRC1 |
---|
684 | Description: Choose smallest floating point value from SRC0 and SRC1, |
---|
685 | and store result to VDST. |
---|
686 | Operation: |
---|
687 | ``` |
---|
688 | VDST = MIN(ASFLOAT(SRC0), ASFLOAT(SRC1)) |
---|
689 | ``` |
---|
690 | |
---|
691 | #### V_MIN_i16 |
---|
692 | |
---|
693 | Opcode VOP2: 50 (0x32) for GCN 1.2 |
---|
694 | Opcode VOP3A: 306 (0x132) for GCN 1.2 |
---|
695 | Syntax: V_MIN_i16 VDST, SRC0, SRC1 |
---|
696 | Description: Choose smallest signed 16-bit value from SRC0 and SRC1, |
---|
697 | and store result to VDST. |
---|
698 | Operation: |
---|
699 | ``` |
---|
700 | VDST = MIN((INT16)SRC0, (INT16)SRC1) |
---|
701 | ``` |
---|
702 | |
---|
703 | #### V_MIN_I32 |
---|
704 | |
---|
705 | Opcode VOP2: 17 (0x11) for GCN 1.0/1.1; 12 (0xc) for GCN 1.2 |
---|
706 | Opcode VOP3A: 273 (0x111) for GCN 1.0/1.1; 268 (0x10c) for GCN 1.2 |
---|
707 | Syntax: V_MIN_I32 VDST, SRC0, SRC1 |
---|
708 | Description: Choose smallest signed value from SRC0 and SRC1, and store result to VDST. |
---|
709 | Operation: |
---|
710 | ``` |
---|
711 | VDST = MIN((INT32)SRC0, (INT32)SRC1) |
---|
712 | ``` |
---|
713 | |
---|
714 | #### V_MIN_LEGACY_F32 |
---|
715 | |
---|
716 | Opcode VOP2: 13 (0xd) for GCN 1.0/1.1 |
---|
717 | Opcode VOP3A: 269 (0x10d) for GCN 1.0/1.1 |
---|
718 | Syntax: V_MIN_LEGACY_F32 VDST, SRC0, SRC1 |
---|
719 | Description: Choose smallest floating point value from SRC0 and SRC1, |
---|
720 | and store result to VDST. If SSRC1 is NaN value then store NaN value to VDST |
---|
721 | (legacy rules for handling NaNs). |
---|
722 | Operation: |
---|
723 | ``` |
---|
724 | if (!ISNAN(ASFLOAT(SRC1))) |
---|
725 | VDST = MIN(ASFLOAT(SRC0), ASFLOAT(SRC1)) |
---|
726 | else |
---|
727 | VDST = NaN |
---|
728 | ``` |
---|
729 | |
---|
730 | #### V_MIN_U16 |
---|
731 | |
---|
732 | Opcode VOP2: 49 (0x31) for GCN 1.2 |
---|
733 | Opcode VOP3A: 305 (0x131) for GCN 1.2 |
---|
734 | Syntax: V_MIN_U16 VDST, SRC0, SRC1 |
---|
735 | Description: Choose smallest unsigned 16-bit value from SRC0 and SRC1, |
---|
736 | and store result to VDST. |
---|
737 | Operation: |
---|
738 | ``` |
---|
739 | VDST = MIN(SRC0&0xffff, SRC1&0xffff) |
---|
740 | ``` |
---|
741 | |
---|
742 | #### V_MIN_U32 |
---|
743 | |
---|
744 | Opcode VOP2: 19 (0x13) for GCN 1.0/1.1; 14 (0xe) for GCN 1.2 |
---|
745 | Opcode VOP3A: 275 (0x113) for GCN 1.0/1.1; 270 (0x10e) for GCN 1.2 |
---|
746 | Syntax: V_MIN_U32 VDST, SRC0, SRC1 |
---|
747 | Description: Choose smallest unsigned value from SRC0 and SRC1, and store result to VDST. |
---|
748 | Operation: |
---|
749 | ``` |
---|
750 | VDST = MIN(SRC0, SRC1) |
---|
751 | ``` |
---|
752 | |
---|
753 | #### V_MUL_LEGACY_F32 |
---|
754 | |
---|
755 | Opcode VOP2: 7 (0x7) for GCN 1.0/1.1; 5 (0x4) for GCN 1.2 |
---|
756 | Opcode VOP3A: 263 (0x107) for GCN 1.0/1.1; 260 (0x104) for GCN 1.2 |
---|
757 | Syntax: V_MUL_LEGACY_F32 VDST, SRC0, SRC1 |
---|
758 | Description: Multiply FP value from SRC0 by FP value from SRC1 and store result to VDST. |
---|
759 | If one of value is 0.0 then always store 0.0 to VDST (do not apply IEEE rules for 0.0*x). |
---|
760 | Operation: |
---|
761 | ``` |
---|
762 | if (ASFLOAT(SRC0)!=0.0 && ASFLOAT(SRC1)!=0.0) |
---|
763 | VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1) |
---|
764 | else |
---|
765 | VDST = 0.0 |
---|
766 | ``` |
---|
767 | |
---|
768 | #### V_MUL_F16 |
---|
769 | |
---|
770 | Opcode VOP2: 34 (0x22) for GCN 1.2 |
---|
771 | Opcode VOP3A: 290 (0x122) for GCN 1.2 |
---|
772 | Syntax: V_MUL_F16 VDST, SRC0, SRC1 |
---|
773 | Description: Multiply FP16 value from SRC0 by FP16 value from SRC1 |
---|
774 | and store result to VDST. |
---|
775 | Operation: |
---|
776 | ``` |
---|
777 | VDST = ASHALF(SRC0) * ASHALF(SRC1) |
---|
778 | ``` |
---|
779 | |
---|
780 | #### V_MUL_F32 |
---|
781 | |
---|
782 | Opcode VOP2: 8 (0x8) for GCN 1.0/1.1; 5 (0x5) for GCN 1.2 |
---|
783 | Opcode VOP3A: 264 (0x108) for GCN 1.0/1.1; 261 (0x105) for GCN 1.2 |
---|
784 | Syntax: V_MUL_F32 VDST, SRC0, SRC1 |
---|
785 | Description: Multiply FP value from SRC0 by FP value from SRC1 and store result to VDST. |
---|
786 | Operation: |
---|
787 | ``` |
---|
788 | VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1) |
---|
789 | ``` |
---|
790 | |
---|
791 | #### V_MUL_HI_I32_I24 |
---|
792 | |
---|
793 | Opcode VOP2: 10 (0xa) for GCN 1.0/1.1; 7 (0x7) for GCN 1.2 |
---|
794 | Opcode VOP3A: 266 (0x10a) for GCN 1.0/1.1; 263 (0x107) for GCN 1.2 |
---|
795 | Syntax: V_MUL_HI_I32_I24 VDST, SRC0, SRC1 |
---|
796 | Description: Multiply 24-bit signed integer value from SRC0 by 24-bit signed value from SRC1 |
---|
797 | and store higher 16-bit of the result to VDST with sign extension. |
---|
798 | Any modifier doesn't affect on result. |
---|
799 | Operation: |
---|
800 | ``` |
---|
801 | INT32 V0 = (INT32)((SRC0&0x7fffff) | (SSRC0&0x800000 ? 0xff800000 : 0)) |
---|
802 | INT32 V1 = (INT32)((SRC1&0x7fffff) | (SSRC1&0x800000 ? 0xff800000 : 0)) |
---|
803 | VDST = ((INT64)V0 * V1)>>32 |
---|
804 | ``` |
---|
805 | |
---|
806 | #### V_MUL_HI_U32_U24 |
---|
807 | |
---|
808 | Opcode VOP2: 12 (0xc) for GCN 1.0/1.1; 9 (0x9) for GCN 1.2 |
---|
809 | Opcode VOP3A: 268 (0x10c) for GCN 1.0/1.1; 265 (0x109) for GCN 1.2 |
---|
810 | Syntax: V_MUL_HI_U32_U24 VDST, SRC0, SRC1 |
---|
811 | Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value |
---|
812 | from SRC1 and store higher 16-bit of the result to VDST. |
---|
813 | Any modifier doesn't affect on result. |
---|
814 | Operation: |
---|
815 | ``` |
---|
816 | VDST = ((UINT64)(SRC0&0xffffff) * (UINT32)(SRC1&0xffffff)) >> 32 |
---|
817 | ``` |
---|
818 | |
---|
819 | #### V_MUL_I32_I24 |
---|
820 | |
---|
821 | Opcode VOP2: 9 (0x9) for GCN 1.0/1.1; 6 (0x6) for GCN 1.2 |
---|
822 | Opcode VOP3A: 265 (0x109) for GCN 1.0/1.1; 262 (0x106) for GCN 1.2 |
---|
823 | Syntax: V_MUL_I32_I24 VDST, SRC0, SRC1 |
---|
824 | Description: Multiply 24-bit signed integer value from SRC0 by 24-bit signed value from SRC1 |
---|
825 | and store result to VDST. Any modifier doesn't affect on result. |
---|
826 | Operation: |
---|
827 | ``` |
---|
828 | INT32 V0 = (INT32)((SRC0&0x7fffff) | (SSRC0&0x800000 ? 0xff800000 : 0)) |
---|
829 | INT32 V1 = (INT32)((SRC1&0x7fffff) | (SSRC1&0x800000 ? 0xff800000 : 0)) |
---|
830 | VDST = V0 * V1 |
---|
831 | ``` |
---|
832 | |
---|
833 | #### V_MUL_LO_U16 |
---|
834 | |
---|
835 | Opcode VOP2: 41 (0x29) for GCN 1.2 |
---|
836 | Opcode VOP3A: 297 (0x129) for GCN 1.2 |
---|
837 | Syntax: V_MUL_LO_U16 VDST, SRC0, SRC1 |
---|
838 | Description: Multiply 16-bit unsigned value from SRC0 by 16-bit unsigned value from SRC1 |
---|
839 | and store 16-bit result to VDST. |
---|
840 | Operation: |
---|
841 | ``` |
---|
842 | VDST = ((SRC0&0Xffff) * (SRC1&0xffff)) & 0xffff |
---|
843 | ``` |
---|
844 | |
---|
845 | #### V_MUL_U32_U24 |
---|
846 | |
---|
847 | Opcode VOP2: 11 (0xb) for GCN 1.0/1.1; 8 (0x8) for GCN 1.2 |
---|
848 | Opcode VOP3A: 267 (0x10b) for GCN 1.0/1.1; 264 (0x108) for GCN 1.2 |
---|
849 | Syntax: V_MUL_U32_U24 VDST, SRC0, SRC1 |
---|
850 | Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value |
---|
851 | from SRC1 and store result to VDST. Any modifier doesn't affect on result. |
---|
852 | Operation: |
---|
853 | ``` |
---|
854 | VDST = (UINT32)(SRC0&0xffffff) * (UINT32)(SRC1&0xffffff) |
---|
855 | ``` |
---|
856 | |
---|
857 | #### V_OR_B32 |
---|
858 | |
---|
859 | Opcode: VOP2: 28 (0x1c) for GCN 1.0/1.1; 20 (0x14) for GCN 1.2 |
---|
860 | Opcode: VOP3A: 284 (0x11c) for GCN 1.0/1.1; 276 (0x114) for GCN 1.2 |
---|
861 | Syntax: V_OR_B32 VDST, SRC0, SRC1 |
---|
862 | Description: Do bitwise OR operation on SRC0 and SRC1, store result to VDST. |
---|
863 | CLAMP and OMOD modifier doesn't affect on result. |
---|
864 | Operation: |
---|
865 | ``` |
---|
866 | VDST = SRC0 | SRC1 |
---|
867 | ``` |
---|
868 | |
---|
869 | #### V_READLANE_B32 |
---|
870 | |
---|
871 | Opcode VOP2: 1 (0x1) for GCN 1.0/1.1 |
---|
872 | Opcode VOP3A: 257 (0x101) for GCN 1.0/1.1 |
---|
873 | Syntax: V_READLANE_B32 SDST, VSRC0, SSRC1 |
---|
874 | Description: Copy one VSRC0 lane value to one SDST. Lane (thread id) choosen from SSRC1&63. |
---|
875 | SSRC1 can be SGPR or M0. Ignores EXEC mask. |
---|
876 | Operation: |
---|
877 | ``` |
---|
878 | SDST = VSRC0[SSRC1 & 63] |
---|
879 | ``` |
---|
880 | |
---|
881 | #### V_SUB_F16 |
---|
882 | |
---|
883 | Opcode VOP2: 32 (0x20) for GCN 1.2 |
---|
884 | Opcode VOP3A: 288 (0x120) for GCN 1.2 |
---|
885 | Syntax: V_SUB_F16 VDST, SRC0, SRC1 |
---|
886 | Description: Subtract FP16 value of SRC1 from FP16 value of SRC0 and store result to VDST. |
---|
887 | Operation: |
---|
888 | ``` |
---|
889 | VDST = ASHALF(SRC0) - ASHALF(SRC1) |
---|
890 | ``` |
---|
891 | |
---|
892 | #### V_SUB_F32 |
---|
893 | |
---|
894 | Opcode VOP2: 4 (0x4) for GCN 1.0/1.1; 2 (0x2) for GCN 1.2 |
---|
895 | Opcode VOP3A: 260 (0x104) for GCN 1.0/1.1; 258 (0x102) for GCN 1.2 |
---|
896 | Syntax: V_SUB_F32 VDST, SRC0, SRC1 |
---|
897 | Description: Subtract FP value of SRC1 from FP value of SRC0 and store result to VDST. |
---|
898 | Operation: |
---|
899 | ``` |
---|
900 | VDST = ASFLOAT(SRC0) - ASFLOAT(SRC1) |
---|
901 | ``` |
---|
902 | |
---|
903 | #### V_SUB_U16 |
---|
904 | |
---|
905 | Opcode VOP2: 39 (0x27) for GCN 1.2 |
---|
906 | Opcode VOP3A: 295 (0x127) for GCN 1.2 |
---|
907 | Syntax: V_SUB_U16 VDST, SRC0, SRC1 |
---|
908 | Description: Subtract unsigned 16-bit value of SRC1 from SRC0 and store |
---|
909 | 16-bit unsigned result to VDST. |
---|
910 | Operation: |
---|
911 | ``` |
---|
912 | VDST = (SRC0 - SRC1) & 0xffff |
---|
913 | ``` |
---|
914 | |
---|
915 | #### V_SUB_I32, V_SUB_U32 |
---|
916 | |
---|
917 | Opcode VOP2: 38 (0x26) for GCN 1.0/1.1; 26 (0x1a) for GCN 1.2 |
---|
918 | Opcode VOP3B: 294 (0x126) for GCN 1.0/1.1; 282 (0x11a) for GCN 1.2 |
---|
919 | Syntax VOP2 GCN 1.0/1.1: V_SUB_I32 VDST, VCC, SRC0, SRC1 |
---|
920 | Syntax VOP3B GCN 1.0/1.1: V_SUB_I32 VDST, SDST(2), SRC0, SRC1 |
---|
921 | Syntax VOP2 GCN 1.2: V_SUB_U32 VDST, VCC, SRC0, SRC1 |
---|
922 | Syntax VOP3B GCN 1.2: V_SUB_U32 VDST, SDST(2), SRC0, SRC1 |
---|
923 | Description: Subtract SRC1 from SRC0 and store result to VDST and store borrow flag to |
---|
924 | SDST (or VCC) bit with number that equal to lane id. SDST is 64-bit. |
---|
925 | Bits for inactive threads in SDST are always zeroed. |
---|
926 | Operation: |
---|
927 | ``` |
---|
928 | UINT64 temp = (UINT64)SRC0 - (UINT64)SRC1 |
---|
929 | VDST = temp |
---|
930 | SDST = 0 |
---|
931 | UINT64 mask = (1ULL<<LANEID) |
---|
932 | SDST = (SDST&~mask) | ((temp>>32) ? mask : 0) |
---|
933 | ``` |
---|
934 | |
---|
935 | #### V_SUBB_U32 |
---|
936 | |
---|
937 | Opcode VOP2: 41 (0x29) for GCN 1.0/1.1; 29 (0x1d) for GCN 1.2 |
---|
938 | Opcode VOP3B: 297 (0x129) for GCN 1.0/1.1; 285 (0x11d) for GCN 1.2 |
---|
939 | Syntax VOP2 GCN 1.0/1.1: V_SUBB_U32 VDST, VCC, SRC0, SRC1, VCC |
---|
940 | Syntax VOP3B GCN 1.2: V_SUBB_U32 VDST, SDST(2), SRC0, SRC1, SSRC2(2) |
---|
941 | Description: Subtract SRC1 with borrow from SRC0, |
---|
942 | and store result to VDST and store carry flag to SDST (or VCC) bit with number |
---|
943 | that equal to lane id. Borrow is stored in SSRC2 bit with number of lane id. |
---|
944 | SDST and SSRC2 are 64-bit. Bits for inactive threads in SDST are always zeroed. |
---|
945 | Operation: |
---|
946 | ``` |
---|
947 | UINT64 mask = (1ULL<<LANEID) |
---|
948 | UINT8 CC = ((SSRC2&mask) ? 1 : 0) |
---|
949 | UINT64 temp = (UINT64)SRC0 - (UINT64)SRC1 - CC |
---|
950 | SDST = 0 |
---|
951 | VDST = temp |
---|
952 | SDST = (SDST&~mask) | ((temp >> 32) ? mask : 0) |
---|
953 | ``` |
---|
954 | |
---|
955 | #### V_SUBBREV_U32 |
---|
956 | |
---|
957 | Opcode VOP2: 42 (0x2a) for GCN 1.0/1.1; 30 (0x1e) for GCN 1.2 |
---|
958 | Opcode VOP3B: 298 (0x12a) for GCN 1.0/1.1; 286 (0x11e) for GCN 1.2 |
---|
959 | Syntax VOP2 GCN 1.0/1.1: V_SUBBREV_U32 VDST, VCC, SRC0, SRC1, VCC |
---|
960 | Syntax VOP3B GCN 1.2: V_SUBBREV_U32 VDST, SDST(2), SRC0, SRC1, SSRC2(2) |
---|
961 | Description: Subtract SRC0 with borrow from SRC1, |
---|
962 | and store result to VDST and store carry flag to SDST (or VCC) bit with number |
---|
963 | that equal to lane id. Borrow is stored in SSRC2 bit with number of lane id. |
---|
964 | SDST and SSRC2 are 64-bit. Bits for inactive threads in SDST are always zeroed. |
---|
965 | Operation: |
---|
966 | ``` |
---|
967 | UINT64 mask = (1ULL<<LANEID) |
---|
968 | UINT8 CC = ((SSRC2&mask) ? 1 : 0) |
---|
969 | UINT64 temp = (UINT64)SRC1 - (UINT64)SRC0 - CC |
---|
970 | SDST = 0 |
---|
971 | VDST = temp |
---|
972 | SDST = (SDST&~mask) | ((temp >> 32) ? mask : 0) |
---|
973 | ``` |
---|
974 | |
---|
975 | #### V_SUBREV_F16 |
---|
976 | |
---|
977 | Opcode VOP2: 33 (0x21) for GCN 1.2 |
---|
978 | Opcode VOP3A: 289 (0x121) for GCN 1.2 |
---|
979 | Syntax: V_SUBREV_F16 VDST, SRC0, SRC1 |
---|
980 | Description: Subtract FP16 value of SRC0 from FP16 value of SRC1 and store result to VDST. |
---|
981 | Operation: |
---|
982 | ``` |
---|
983 | VDST = ASHALF(SRC1) - ASHALF(SRC0) |
---|
984 | ``` |
---|
985 | |
---|
986 | #### V_SUBREV_F32 |
---|
987 | |
---|
988 | Opcode VOP2: 5 (0x5) for GCN 1.0/1.1; 2 (0x3) for GCN 1.2 |
---|
989 | Opcode VOP3A: 261 (0x105) for GCN 1.0/1.1; 259 (0x103) for GCN 1.2 |
---|
990 | Syntax: V_SUBREV_F32 VDST, SRC0, SRC1 |
---|
991 | Description: Subtract FP value of SRC0 from FP value of SRC1 and store result to VDST. |
---|
992 | Operation: |
---|
993 | ``` |
---|
994 | VDST = ASFLOAT(SRC1) - ASFLOAT(SRC0) |
---|
995 | ``` |
---|
996 | |
---|
997 | #### V_SUBREV_I32, V_SUBREV_U32 |
---|
998 | |
---|
999 | Opcode VOP2: 39 (0x27) for GCN 1.0/1.1; 27 (0x1b) for GCN 1.2 |
---|
1000 | Opcode VOP3B: 295 (0x127) for GCN 1.0/1.1; 283 (0x11b) for GCN 1.2 |
---|
1001 | Syntax VOP2 GCN 1.0/1.1: V_SUBREV_I32 VDST, VCC, SRC0, SRC1 |
---|
1002 | Syntax VOP3B GCN 1.0/1.1: V_SUBREV_I32 VDST, SDST(2), SRC0, SRC1 |
---|
1003 | Syntax VOP2 GCN 1.2: V_SUBREV_U32 VDST, VCC, SRC0, SRC1 |
---|
1004 | Syntax VOP3B GCN 1.2: V_SUBREV_U32 VDST, SDST(2), SRC0, SRC1 |
---|
1005 | Description: Subtract SRC0 from SRC1 and store result to VDST and store borrow flag to |
---|
1006 | SDST (or VCC) bit with number that equal to lane id. SDST is 64-bit. |
---|
1007 | Bits for inactive threads in SDST are always zeroed. |
---|
1008 | Operation: |
---|
1009 | ``` |
---|
1010 | UINT64 temp = (UINT64)SRC1 - (UINT64)SRC0 |
---|
1011 | VDST = temp |
---|
1012 | SDST = 0 |
---|
1013 | UINT64 mask = (1ULL<<LANEID) |
---|
1014 | SDST = (SDST&~mask) | ((temp>>32) ? mask : 0) |
---|
1015 | ``` |
---|
1016 | |
---|
1017 | #### V_SUBREV_U16 |
---|
1018 | |
---|
1019 | Opcode VOP2: 40 (0x28) for GCN 1.2 |
---|
1020 | Opcode VOP3A: 296 (0x128) for GCN 1.2 |
---|
1021 | Syntax: V_SUBREV_U16 VDST, SRC0, SRC1 |
---|
1022 | Description: Subtract unsigned 16-bit value of SRC0 from SRC1 and store |
---|
1023 | 16-bit unsigned result to VDST. |
---|
1024 | Operation: |
---|
1025 | ``` |
---|
1026 | VDST = (SRC1 - SRC0) & 0xffff |
---|
1027 | ``` |
---|
1028 | |
---|
1029 | #### V_XOR_B32 |
---|
1030 | |
---|
1031 | Opcode: VOP2: 29 (0x1d) for GCN 1.0/1.1; 21 (0x15) for GCN 1.2 |
---|
1032 | Opcode: VOP3A: 285 (0x11d) for GCN 1.0/1.1; 277 (0x115) for GCN 1.2 |
---|
1033 | Syntax: V_XOR_B32 VDST, SRC0, SRC1 |
---|
1034 | Description: Do bitwise XOR operation on SRC0 and SRC1, store result to VDST. |
---|
1035 | CLAMP and OMOD modifier doesn't affect on result. |
---|
1036 | Operation: |
---|
1037 | ``` |
---|
1038 | VDST = SRC0 ^ SRC1 |
---|
1039 | ``` |
---|
1040 | |
---|
1041 | #### V_WRITELANE_B32 |
---|
1042 | |
---|
1043 | Opcode VOP2: 2 (0x2) for GCN 1.0/1.1 |
---|
1044 | Opcode VOP3A: 258 (0x102) for GCN 1.0/1.1 |
---|
1045 | Syntax: V_WRITELANE_B32 VDST, VSRC0, SSRC1 |
---|
1046 | Description: Copy SGPR to one lane of VDST. Lane choosen (thread id) from SSRC1&63. |
---|
1047 | SSRC1 can be SGPR or M0. Ignores EXEC mask. |
---|
1048 | Operation: |
---|
1049 | ``` |
---|
1050 | VDST[SSRC1 & 63] = SSRC0 |
---|
1051 | ``` |
---|