Changeset 1674 in CLRX


Ignore:
Timestamp:
Nov 7, 2015, 4:13:39 PM (5 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Fixed register's symbol parsing (correct condition for handling execz/scc/vccz).
Tests for testing a register's symbols.

Location:
CLRadeonExtender/trunk
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/amdasm/GCNAsmHelpers.cpp

    r1673 r1674  
    9090        if ((vsflags == INSTROP_VREGS && rstart >= 256 && rend >= 256) ||
    9191            (vsflags == INSTROP_SREGS && rstart < 256 && rend < 256 &&
    92             /* if ssource and regs is vccz/execz/scc or
    93              *    no ssource and not vccz/execz/scc */
    94             (((flags&INSTROP_SSOURCE)==0) ^ (rstart==251 || rstart==252 || rstart==253))) ||
     92            (((flags&INSTROP_SSOURCE)!=0) || (rstart!=251 && rstart!=252 && rstart!=253))) ||
    9593            vsflags == (INSTROP_VREGS|INSTROP_SREGS))
    9694        {
     
    796794    if (instrOpMask & (INSTROP_SREGS|INSTROP_VREGS))
    797795    {
    798         if (!parseSymRegRange(asmr, linePtr, operand.range, arch, regsNum, INSTROP_SREGS|
    799                     INSTROP_VREGS|(instrOpMask&INSTROP_SSOURCE)|alignFlags, false))
     796        if (!parseSymRegRange(asmr, linePtr, operand.range, arch, regsNum,
     797                (instrOpMask&((INSTROP_SREGS|INSTROP_VREGS|INSTROP_SSOURCE))) |
     798                    alignFlags, false))
    800799            return false;
    801800        if (operand)
  • CLRadeonExtender/trunk/tests/amdasm/GCNAsmOpc11.cpp

    r1662 r1674  
    4040    { "zx=21; ss=2; b=60;s_add_u32  s[zx], s[ss*2], s[b+1]",
    4141            0x80153d04U, 0, false, true, "" },
     42    /* register's symbols */
     43    { "zx=%s[20:23]; ss=%s4; b=%s[57:67];s_add_u32  zx[1], ss, b[4]",
     44            0x80153d04U, 0, false, true, "" },
     45    { "xv=2; zx=%s[xv+18:xv+19]; ss=%s[xv+2]; b=%s[xv+55:xv+65];"
     46        "s_add_u32  zx[1], ss, b[4]", 0x80153d04U, 0, false, true, "" },
     47    { "zx=%s[20:23]; ss=%execz; b=%s[57:67];s_add_u32  zx[1], ss, b[4]",
     48            0x80153dfcU, 0, false, true, "" },
    4249    { "    s_add_u32  s21, s4, 0", 0x80158004U, 0, false, true, "" },
    4350    { "    s_add_u32  s21, s4, 1", 0x80158104U, 0, false, true, "" },
     
    143150    { "  s_add_u32  s35, 400000, 1111116", 0, 0, false, false,
    144151        "test.s:1:27: Error: Only one literal can be used in instruction\n" },
     152    { "    s_xor_b64  s[30:31], vcc_hi, s[14:15]", 0, 0, false, false,
     153        "test.s:1:26: Error: Required 2 scalar registers\n" },
     154    { "k=%s5; s_xor_b64  s[30:31], k, s[14:15]", 0, 0, false, false,
     155        "test.s:1:29: Error: Required 2 scalar registers\n" },
     156    { "k=%execz; s_xor_b64  s[30:31], k, s[14:15]", 0, 0, false, false,
     157        "test.s:1:32: Error: Required 2 scalar registers\n" },
     158    { "k=%v[10:11]; s_xor_b64  s[30:31], k, s[14:15]", 0, 0, false, false,
     159        "test.s:1:35: Error: Expression have register symbol\n"
     160        "test.s:1:35: Error: Expected ',' before argument\n" },
    145161    /* SOP2 encodings */
    146162    { "    s_sub_u32  s21, s4, s61", 0x80953d04U, 0, false, true, "" },
     
    535551    { "    v_writelane_b32  v26, v21, s94", 0x0434bd15U, 0, false, true, "" },
    536552    { "    v_add_f32  v154, v21, v107", 0x0734d715U, 0, false, true, "" },
     553    /* register names */
     554    { "tx=%v21; ty=%v107; v_add_f32  v154, tx, ty", 0x0734d715U, 0, false, true, "" },
     555    { "tx=%v[16:23]; ty=%v107; v_add_f32  v154, tx[5], ty",
     556        0x0734d715U, 0, false, true, "" },
     557    { "tx=%s21; v_add_f32  v154, tx, v107", 0x0734d615U, 0, false, true, "" },
    537558    { "    v_add_f32  v154, s21, v107", 0x0734d615U, 0, false, true, "" },
    538559    { "    v_add_f32  v154, v21, v107 vop3", 0xd206009aU, 0x0002d715U, true, true, "" },
     
    616637    { "    v_add_f32  v154, s2, s4", 0, 0, false, false,
    617638        "test.s:1:5: Error: More than one SGPR to read in instruction\n" },
     639    /* out holds scalar register (not vector) */
     640    { "out=%s64;v_add_f32  out, s21, v107", 0, 0, false, false,
     641        "test.s:1:21: Error: Expected 1 vector register\n" },
     642    { "out=%v[64:65];v_add_f32  out, s21, v107", 0, 0, false, false,
     643        "test.s:1:26: Error: Required 1 vector register\n" },
    618644    /* OMOD already defined */
    619645    { "    v_add_f32  v154, v21, v107 mul:4 div:2", 0xd206009aU, 0x1802d715U, true, true,
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