Changeset 1708 in CLRX


Ignore:
Timestamp:
Nov 13, 2015, 11:29:43 PM (5 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Doc updates: Table of SOP2 instructions, GCN 1.2 encoding for S_ABSDIFF_I32.

File:
1 edited

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  • CLRadeonExtender/trunk/doc/GcnInstrsSop2.md

    r1707 r1708  
    1919List of the instructions by opcode:
    2020
    21 Opcode | Mnemonic
    22 -------|---------------
    23 0      | S_ADD_U32
    24 1      | S_SUB_U32
    25 2      | S_ADD_I32
    26 3      | S_SUB_I32
    27 4      | S_ADDC_U32
    28 5      | S_SUBB_U32
    29 6      | S_MIN_I32
    30 7      | S_MIN_U32
    31 8      | S_MAX_I32
    32 9      | S_MAX_U32
    33 10     | S_CSELECT_B32
    34 11     | S_CSELECT_B64
    35 14     | S_AND_B32
    36 15     | S_AND_B64
    37 16     | S_OR_B32
    38 17     | S_OR_B64
    39 18     | S_XOR_B32
    40 19     | S_XOR_B64
     21 GCN 1.0   |  GCN 1.1  | GCN 1.2    | Mnemonic
     22-----------|-----------|------------|---------------
     23 0 (0x0)   | 0 (0x0)   | 0 (0x0)    | S_ADD_U32
     24 1 (0x1)   | 1 (0x1)   | 1 (0x1)    | S_SUB_U32
     25 2 (0x2)   | 2 (0x2)   | 2 (0x2)    | S_ADD_I32
     26 3 (0x3)   | 3 (0x3)   | 3 (0x3)    | S_SUB_I32
     27 4 (0x4)   | 4 (0x4)   | 4 (0x4)    | S_ADDC_U32
     28 5 (0x5)   | 5 (0x5)   | 5 (0x5)    | S_SUBB_U32
     29 6 (0x6)   | 6 (0x6)   | 6 (0x6)    | S_MIN_I32
     30 7 (0x7)   | 7 (0x7)   | 7 (0x7)    | S_MIN_U32
     31 8 (0x8)   | 8 (0x8)   | 8 (0x8)    | S_MAX_I32
     32 9 (0x9)   | 9 (0x9)   | 9 (0x9)    | S_MAX_U32
     33 10 (0xa)  | 10 (0xa)  | 10 (0xa)   | S_CSELECT_B32
     34 11 (0xb)  | 11 (0xb)  | 11 (0xb)   | S_CSELECT_B64
     35 14 (0xe)  | 14 (0xe)  | 12 (0xc)   | S_AND_B32
     36 15 (0xf)  | 15 (0xf)  | 13 (0xd)   | S_AND_B64
     37 16 (0x10) | 16 (0x10) | 14 (0xe)   | S_OR_B32
     38 17 (0x11) | 17 (0x11) | 15 (0xf)   | S_OR_B64
     39 18 (0x12) | 18 (0x12) | 16 (0x10)  | S_XOR_B32
     40 19 (0x13) | 19 (0x13) | 17 (0x11)  | S_XOR_B64
     41 20 (0x14) | 20 (0x14) | 18 (0x12)  | SS_ANDN2_B32
     42 21 (0x15) | 21 (0x15) | 19 (0x13)  | SS_ANDN2_B64
     43 22 (0x16) | 22 (0x16) | 20 (0x14)  | SS_ORN2_B32
     44 23 (0x17) | 23 (0x17) | 21 (0x15)  | SS_ORN2_B64
     45 24 (0x18) | 24 (0x18) | 22 (0x16)  | SS_NAND_B32
     46 25 (0x19) | 25 (0x19) | 23 (0x17)  | SS_NAND_B64
     47 26 (0x1a) | 26 (0x1a) | 24 (0x18)  | SS_NOR_B32
     48 27 (0x1b) | 27 (0x1b) | 25 (0x19)  | SS_NOR_B64
     49 28 (0x1c) | 28 (0x1c) | 26 (0x1a)  | SS_XNOR_B32
     50 29 (0x1d) | 29 (0x1d) | 27 (0x1b)  | SS_XNOR_B64
     51 30 (0x1e) | 30 (0x1e) | 28 (0x1c)  | SS_LSHL_B32
     52 31 (0x1f) | 31 (0x1f) | 29 (0x1d)  | SS_LSHL_B64
     53 32 (0x20) | 32 (0x20) | 30 (0x1e)  | SS_LSHR_B32
     54 33 (0x21) | 33 (0x21) | 31 (0x1f)  | SS_LSHR_B64
     55 34 (0x22) | 34 (0x22) | 32 (0x20)  | SS_ASHR_I32
     56 35 (0x23) | 35 (0x23) | 33 (0x21)  | SS_ASHR_I64
     57 36 (0x24) | 36 (0x24) | 34 (0x22)  | SS_BFM_B32
     58 37 (0x25) | 37 (0x25) | 35 (0x23)  | SS_BFM_B64
     59 38 (0x26) | 38 (0x26) | 36 (0x24)  | SS_MUL_I32
     60 39 (0x27) | 39 (0x27) | 37 (0x25)  | SS_BFE_U32
     61 40 (0x28) | 40 (0x28) | 38 (0x26)  | SS_BFE_I32
     62 41 (0x29) | 41 (0x29) | 39 (0x27)  | SS_BFE_U64
     63 42 (0x2a) | 42 (0x2a) | 40 (0x28)  | SS_BFE_I64
     64 43 (0x2b) | 43 (0x2b) | 41 (0x29)  | SS_CBRANCH_G_FORK
     65 44 (0x2c) | 44 (0x2c) | 42 (0x2a)  | S_ABSDIFF_I32
     66 --        | --        | 43 (0x2b)  | S_RFE_RESTORE_B64
    4167
    4268### Instruction set
     
    4571
    4672#### S_ABSDIFF_I32
    47 Opcode: 44 (0x2c)
     73Opcode: 44 (0x2c) for GCN 1.0/11; 42 (0x2a) for GCN 1.2 
    4874Syntax: S_ABSDIFF_I32 SDST, SSRC0, SSRC1 
    4975Description: Compute absolute difference from SSRC0 and SSRC1 and store result to SDST.
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