Changeset 1714 in CLRX


Ignore:
Timestamp:
Nov 14, 2015, 7:51:34 PM (5 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Updated GcnInstrsSopk.md: Added S_CBRANCH_I_FORK, small fixes.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/doc/GcnInstrsSopk.md

    r1713 r1714  
    1212Syntax for almost instructions: INSTRUCTION SDST, SIMM16
    1313
    14 SIMM16 - signed 16-bit immediate. IMM16 - unsigned 16-bit immediate.
     14SIMM16 - signed 16-bit immediate. IMM16 - unsigned 16-bit immediate. 
     15RELADDR - relative offset to this instruction (can be label or relative expresion).
     16RELADDR = NEXTPC + SIMM16, NEXTPC - PC for next instruction.
    1517
    1618List of the instructions by opcode:
     
    5860```
    5961
     62#### S_CBRANCH_I_FORK
     63
     64Opcode: 17 (0x11) for GCN 1.0/1.1; 16 (0x10) for GCN 1.2 
     65Syntax: S_CBRANCH_I_FORK SSRC0(2), RELADDR 
     66Description: Fork control flow to passed and failed condition, jump to address RELADDR for
     67passed conditions. Make two masks: for passed conditions (EXEC & SSRC0),
     68for failed conditions: (EXEC & ~SSRC0).
     69Choose way that have smallest active threads and push data for second way to control stack
     70(EXEC mask, jump address). Control stack pointer is stored in CSP
     71(3 last bits in MODE register). One entry of the stack have 4 dwords.
     72This instruction doesn't work if SSRC0 is immediate value. 
     73Operation: 
     74```
     75UINT64 passes = (EXEC & SSRC0)
     76UINT64 failures = (EXEC & ~SSRC0)
     77if (passes == EXEC)
     78    PC = SSRC1
     79else if (failures == EXEC)
     80    PC += 4
     81else if (BITCOUNT(failures) < BITCOUNT(passes)) {
     82    EXEC = failures
     83    SGPR[CSP*4:CSP*4+1] = passes
     84    SGPR[CSP*4+2:CSP*4+3] = RELADDR
     85    CSP++
     86    PC += 4 /* jump to failure */
     87} else {
     88    EXEC = passes
     89    SGPR[CSP*4:CSP*4+1] = failures
     90    SGPR[CSP*4+2:CSP*4+3] = PC+4
     91    CSP++
     92    PC = RELADDR /* jump to passes */
     93}
     94```
     95
    6096#### S_CMOVK_I32
    6197
     
    211247```
    212248
    213 #### S_MUL_I32
     249#### S_MULK_I32
    214250
    215251Opcode: 16 (0x10) for GCN 1.0/1.1; 15 (0xf) for GCN 1.2 
Note: See TracChangeset for help on using the changeset viewer.