Changeset 1715 in CLRX


Ignore:
Timestamp:
Nov 14, 2015, 10:55:08 PM (5 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Doc updates: Added hardware register list, added S_GETREG_B32 and S_SETREG_*

Location:
CLRadeonExtender/trunk/doc
Files:
2 edited

Legend:

Unmodified
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  • CLRadeonExtender/trunk/doc/GcnInstrsSopk.md

    r1714 r1715  
    237237```
    238238
     239#### S_GETREG_B32
     240
     241Opcode: 18 (0x12) for GCN1.0/1.1; 17 (0x11) for GCN 1.2 
     242Syntax: S_GETREG_B32 SDST, HWREG(HWREGNAME, BITOFFSET, BITSIZE) 
     243Description: Store hardware register part to SDST. BITOFFSET (0-31) is first bit in
     244hardware register, BITSIZE (1-32) is number of bits to extract. 
     245Operation: 
     246```
     247SDST = (HWREG >> BITOFFSET) & ((1U << BITSIZE) - 1U)
     248```
     249
    239250#### S_MOVK_I32
    240251
     
    256267SDST = SDST * SIMM16
    257268```
     269
     270#### S_SETREG_B32
     271
     272Opcode: 19 (0x13) for GCN1.0/1.1; 18 (0x12) for GCN 1.2 
     273Syntax: S_SETREG_B32 HWREG(HWREGNAME, BITOFFSET, BITSIZE), SDST 
     274Description: Store value from SDST to part of the hardware register.
     275BITOFFSET (0-31) is first bit in hardware register,
     276BITSIZE (1-32) is number of bits to store. 
     277Operation: 
     278```
     279UINT32 mask = ((1U<<BITSIZE) - 1U) << BITOFFSET
     280HWREG = (HWREG & ~mask) | ((SDST<<BITOFFSET) & mask)
     281```
     282
     283#### S_SETREG_IMM32_B32
     284
     285Opcode: 21 (0x15) for GCN1.0/1.1; 20 (0x14) for GCN 1.2 
     286Syntax: S_SETREG_B32 HWREG(HWREGNAME, BITOFFSET, BITSIZE), IMM32 
     287Description: Store value from IMM32 to part of the hardware register.
     288BITOFFSET (0-31) is first bit in hardware register,
     289BITSIZE (1-32) is number of bits to store. IMM32 is immediate 32-bit value after
     290instruction dword. 
     291Operation: 
     292```
     293UINT32 mask = ((1U<<BITSIZE) - 1U) << BITOFFSET
     294HWREG = (HWREG & ~mask) | ((IMM32<<BITOFFSET) & mask)
     295```
  • CLRadeonExtender/trunk/doc/GcnOperands.md

    r1698 r1715  
    7676Syntax: S_SUB_I32 SDST, SSRC0, SSRC1 
    7777Syntax: S_AND_B64 SDST(2), SSRC0(2), SSRC1(2) 
     78
     79### Hardware registers
     80
     81These register could be read or written by S_GETREG_\* and S_SETREG_\* instruction.
     82
     83List of hardware registers:
     84
     85* GPR_ALLOC, HWREG_GPR_ALLOC -
     86* HW_ID, HWREG_HW_ID -
     87* IB_DBG0, HWREG_DBG0 -
     88* IB_STS, HWREG_IB_STS -
     89* INST_DW0, HWREG_INST_DW0 -
     90* INST_DW1, HWREG_INST_DW1 -
     91* LDS_ALLOC, HWREG_LDS_ALLOC -
     92* MODE, HWREG_MODE -
     93* PC_HI, HWREG_PC_HI -
     94* PC_LO, HWREG_PC_LO -
     95* STATUS, HWREG_STATUS -
     96* TRAPSTS, HWREG_TRAPSTS -
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