Changeset 1721 in CLRX


Ignore:
Timestamp:
Nov 16, 2015, 4:59:39 PM (5 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Doc updates: Fixes in GcnInstrSop1.md and GcnInsa?.md.

Location:
CLRadeonExtender/trunk/doc
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/doc/GcnInstrsSop1.md

    r1720 r1721  
    7777Alphabetically sorted instruction list:
    7878
     79#### S_ABS_I32
     80
     81Opcode: 52 (0x34) for GCN 1.0/1.1; 48 (0x30) for GCN 1.2 
     82Syntax: S_NOT_B32 SDST, SSRC0 
     83Description: Store absolute signed value of the SSRC0 into SDST.
     84If result is non-zero, store 1 to SCC, otherwise store 0 to SCC. 
     85Operation: 
     86```
     87SDST = ABS(SSRC0)
     88SCC = SDST!=0
     89```
     90
    7991#### S_AND_SAVEEXEC_B64
    8092
     
    232244Description: Join conditional branch that begin from S_CBRANCH_*_FORK. If control stack
    233245pointer have same value as SSRC0 then do nothing and jump to next instruction, otherwise
    234 pop from control stack value program counter and EXEC value. 
     246pop from control stack program counter and EXEC value. 
    235247Operation: 
    236248```
     
    411423```
    412424
    413 #### S_MOV_B32
    414 
    415 Opcode: 3 (0x3) for GCN 1.0/1.1; 0 (0x0) for GCN 1.2 
    416 Syntax: S_MOV_B32 SDST, SSRC0 
    417 Description: Move value of SSRC0 into SDST. 
    418 Operation: 
    419 ```
    420 SDST = SSRC0
    421 ```
    422 
    423425#### S_MOVRELD_B32
    424426
     
    465467```
    466468
     469#### S_NAND_SAVEEXEC_B64
     470
     471Opcode: 41 (0x29) for GCN 1.0/1.1; 37 (0x25) for GCN 1.2 
     472Syntax: S_NAND_SAVEEXEC_B64 SDST(2), SDST(2) 
     473Description: Store EXEC register to SDST. Make bitwise NAND on SSRC0 and EXEC
     474and store result to EXEC. If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
     475SDST and SSRC0 are 64-bit. 
     476Operation: 
     477```
     478SDST = EXEC
     479EXEC = ~(SSRC0 & EXEC)
     480SCC = EXEC!=0
     481```
     482
     483#### S_NOR_SAVEEXEC_B64
     484
     485Opcode: 42 (0x2a) for GCN 1.0/1.1; 38 (0x26) for GCN 1.2 
     486Syntax: S_NOR_SAVEEXEC_B64 SDST(2), SDST(2) 
     487Description: Store EXEC register to SDST. Make bitwise NOR on SSRC0 and EXEC
     488and store result to EXEC. If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
     489SDST and SSRC0 are 64-bit. 
     490Operation: 
     491```
     492SDST = EXEC
     493EXEC = ~(SSRC0 | EXEC)
     494SCC = EXEC!=0
     495```
     496
    467497#### S_NOT_B32
    468498
     
    475505SDST = ~SSRC0
    476506SCC = SDST!=0
    477 ```
    478 #### S_NAND_SAVEEXEC_B64
    479 
    480 Opcode: 41 (0x29) for GCN 1.0/1.1; 37 (0x25) for GCN 1.2 
    481 Syntax: S_NAND_SAVEEXEC_B64 SDST(2), SDST(2) 
    482 Description: Store EXEC register to SDST. Make bitwise NAND on SSRC0 and EXEC
    483 and store result to EXEC. If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
    484 SDST and SSRC0 are 64-bit. 
    485 Operation: 
    486 ```
    487 SDST = EXEC
    488 EXEC = ~(SSRC0 & EXEC)
    489 SCC = EXEC!=0
    490 ```
    491 
    492 #### S_NOR_SAVEEXEC_B64
    493 
    494 Opcode: 42 (0x2a) for GCN 1.0/1.1; 38 (0x26) for GCN 1.2 
    495 Syntax: S_NOR_SAVEEXEC_B64 SDST(2), SDST(2) 
    496 Description: Store EXEC register to SDST. Make bitwise NOR on SSRC0 and EXEC
    497 and store result to EXEC. If result is non-zero, store 1 to SCC, otherwise store 0 to SCC.
    498 SDST and SSRC0 are 64-bit. 
    499 Operation: 
    500 ```
    501 SDST = EXEC
    502 EXEC = ~(SSRC0 | EXEC)
    503 SCC = EXEC!=0
    504507```
    505508
  • CLRadeonExtender/trunk/doc/GcnIsa.md

    r1717 r1721  
    2626
    2727* SEXT64(v) - sign extend to 64-bit from any signed value
    28 * ABS(v) - absolute value
     28* ABS(v) - absolute value, if value is maximum negative then returns this value.
    2929* BITCOUNT(v) - count 1's bits in value
    3030* REVBIT(v) - reverse bits (n bit goes to BITS-n-1 bit,
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