Changeset 1735 in CLRX


Ignore:
Timestamp:
Nov 20, 2015, 8:20:19 PM (5 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Update VOP2 instruction list. Fixed encoding V_WRITELANE_B32.

Location:
CLRadeonExtender/trunk
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/amdasm/GCNAssembler.cpp

    r1696 r1735  
    965965        sgprsReaded++;
    966966   
    967     if (sgprsReaded >= 2)
     967    if (gcnInsn.code1!=2 /* if no v_writelane_b32 */ && sgprsReaded >= 2)
    968968    {   /* include VCCs (???) */
    969969        asmr.printError(instrPlace, "More than one SGPR to read in instruction");
     
    15571557            numSgprToRead++;
    15581558       
    1559         if (numSgprToRead>=2)
     1559        if ((!isGCN12 || gcnInsn.code1!=650 /* if not v_write_lane_b32 */) &&
     1560            numSgprToRead>=2)
    15601561        {
    15611562            asmr.printError(instrPlace, "More than one SGPR to read in instruction");
  • CLRadeonExtender/trunk/doc/GcnInstrsVop2.md

    r1734 r1735  
    104104Syntax VOP3a: V_CNDMASK_B32 VDST, SRC0, SRC1, SSRC2(2) 
    105105Description: If bit for current thread of VCC or SDST is set then store SRC1 to VDST,
    106 otherwise store SRC0 to VDST.
     106otherwise store SRC0 to VDST. CLAMP and OMOD modifier doesn't affect on result.
    107107Operation:
    108108```
    109109VDST = SSRC2&(1ULL<<THREADID) ? SRC1 : SRC0
     110```
     111
     112#### V_READLANE_B32
     113
     114Opcode VOP2: 1 (0x1) for GCN 1.0/1.1 
     115Opcode VOP3a: 257 (0x101) for GCN 1.0/1.1 
     116Syntax: V_READLANE_B32 SDST, VSRC0, SSRC1 
     117Description: Copy one VSRC0 lane value to one SDST. Lane (thread id) choosen from SSRC1&63.
     118SSRC1 can be SGPR or M0. 
     119Operation: 
     120```
     121SDST = VSRC0[SSRC1 & 63]
     122```
     123
     124#### V_WRITELANE_B32
     125
     126Opcode VOP2: 2 (0x2) for GCN 1.0/1.1 
     127Opcode VOP3a: 258 (0x102) for GCN 1.0/1.1 
     128Syntax: V_WRITELANE_B32 VDST, VSRC0, SSRC1 
     129Description: Copy SGPR to one lane of VDST. Lane choosen (thread id) from SSRC1&63.
     130SSRC1 can be SGPR or M0. 
     131Operation: 
     132```
     133VDST[SSRC1 & 63] = SSRC0
    110134```
    111135
     
    115139Opcode VOP3a: 260 (0x104) for GCN 1.0/1.1; 258 (0x102) for GCN 1.2 
    116140Syntax: V_SUB_F32 VDST, SRC0, SRC1 
    117 Description: Subtract two FP value from SRC0 and SRC1 and store result to VDST. 
     141Description: Subtract FP value from SRC0 and FP value from SRC1 and store result to VDST. 
    118142Operation: 
    119143```
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