Changeset 1737 in CLRX


Ignore:
Timestamp:
Nov 20, 2015, 11:47:44 PM (5 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Doc updates: Updates list of the VOP2 instructions (GcnInstrsVop2.md).

File:
1 edited

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  • CLRadeonExtender/trunk/doc/GcnInstrsVop2.md

    r1735 r1737  
    5959Negation and absolute value can be combined: `-ABS(V0)`. Modifiers CLAMP and
    6060OMOD (MUL:2, MUL:4 and DIV:2) can be given in random order.
     61
     62Limitations for operands:
     63
     64* only one SGPR can be read by instruction. Multiple occurrences of this same
     65SGPR is allowed
     66* only one literal constant can be used, and only when a SGPR or M0 is not used in
     67source operands
     68* only SRC0 can holds LDS_DIRECT
    6169
    6270VOP2 opcodes (0-63) are reflected in VOP3 in range: 256-319.
     
    105113Description: If bit for current thread of VCC or SDST is set then store SRC1 to VDST,
    106114otherwise store SRC0 to VDST. CLAMP and OMOD modifier doesn't affect on result. 
    107 Operation:
     115Operation: 
    108116```
    109117VDST = SSRC2&(1ULL<<THREADID) ? SRC1 : SRC0
     118```
     119
     120#### V_MAC_LEGACY_F32
     121
     122Opcode VOP2: 6 (0x6) for GCN 1.0/1.1
     123Opcode VOP3a: 262 (0x106) for GCN 1.0/1.1
     124Syntax: V_MUL_LEGACY_F32 VDST, SRC0, SRC1 
     125Description: Multiply FP value from SRC0 by FP value from SRC1 and add result to VDST.
     126If one of value is 0.0 then always do not change VDST (do not apply IEEE rules for 0.0*x). 
     127Operation: 
     128```
     129if ((FLOAT)SRC0!=0.0 && (FLOAT)SRC1!=0.0)
     130    VDST = (FLOAT)SRC0 * (FLOAT)SRC1 + (FLOAT)VDST
     131```
     132
     133#### V_MUL_LEGACY_F32
     134
     135Opcode VOP2: 7 (0x7) for GCN 1.0/1.1; 5 (0x4) for GCN 1.2 
     136Opcode VOP3a: 263 (0x107) for GCN 1.0/1.1; 260 (0x104) for GCN 1.2 
     137Syntax: V_MUL_LEGACY_F32 VDST, SRC0, SRC1 
     138Description: Multiply FP value from SRC0 by FP value from SRC1 and store result to VDST.
     139If one of value is 0.0 then always store 0.0 to VDST (do not apply IEEE rules for 0.0*x). 
     140Operation: 
     141```
     142if ((FLOAT)SRC0!=0.0 && (FLOAT)SRC1!=0.0)
     143    VDST = (FLOAT)SRC0 * (FLOAT)SRC1
     144else
     145    VDST = 0.0
     146```
     147
     148#### V_MUL_F32
     149
     150Opcode VOP2: 8 (0x8) for GCN 1.0/1.1; 5 (0x5) for GCN 1.2 
     151Opcode VOP3a: 264 (0x108) for GCN 1.0/1.1; 261 (0x105) for GCN 1.2 
     152Syntax: V_MUL_F32 VDST, SRC0, SRC1 
     153Description: Multiply FP value from SRC0 by FP value from SRC1 and store result to VDST. 
     154Operation: 
     155```
     156VDST = (FLOAT)SRC0 * (FLOAT)SRC1
     157```
     158
     159#### V_MUL_HI_I32_24
     160
     161Opcode VOP2: 10 (0xa) for GCN 1.0/1.1; 7 (0x7) for GCN 1.2 
     162Opcode VOP3a: 266 (0x10a) for GCN 1.0/1.1; 263 (0x107) for GCN 1.2 
     163Syntax: V_MUL_HI_I32_24 VDST, SRC0, SRC1 
     164Description: Multiply 24-bit signed integer value from SRC0 by 24-bit signed value from SRC1
     165and store higher 16-bit of the result to VDST with sign extension.
     166Any modifier doesn't affect on result. 
     167Operation: 
     168```
     169INT32 V0 = (INT32)((SRC0&0x7fffff) | (SSRC0&0x800000 ? 0xff800000 : 0))
     170INT32 V1 = (INT32)((SRC1&0x7fffff) | (SSRC1&0x800000 ? 0xff800000 : 0))
     171VDST = ((INT64)V0 * V1)>>32
     172```
     173
     174#### V_MUL_HI_U32_U24
     175
     176Opcode VOP2: 12 (0xc) for GCN 1.0/1.1; 9 (0x9) for GCN 1.2 
     177Opcode VOP3a: 268 (0x10c) for GCN 1.0/1.1; 265 (0x109) for GCN 1.2 
     178Syntax: V_MUL_HI_U32_U24 VDST, SRC0, SRC1 
     179Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value
     180from SRC1 and store higher 16-bit of the result to VDST.
     181Any modifier doesn't affect to result. 
     182Operation: 
     183```
     184VDST = ((UINT64)(SRC0&0xffffff) * (UINT32)(SRC1&0xffffff)) >> 32
     185```
     186
     187#### V_MUL_I32_I24
     188
     189Opcode VOP2: 9 (0x9) for GCN 1.0/1.1; 6 (0x6) for GCN 1.2 
     190Opcode VOP3a: 265 (0x109) for GCN 1.0/1.1; 262 (0x106) for GCN 1.2 
     191Syntax: V_MUL_I32_I24 VDST, SRC0, SRC1 
     192Description: Multiply 24-bit signed integer value from SRC0 by 24-bit signed value from SRC1
     193and store result to VDST. Any modifier doesn't affect to result. 
     194Operation: 
     195```
     196INT32 V0 = (INT32)((SRC0&0x7fffff) | (SSRC0&0x800000 ? 0xff800000 : 0))
     197INT32 V1 = (INT32)((SRC1&0x7fffff) | (SSRC1&0x800000 ? 0xff800000 : 0))
     198VDST = V0 * V1
     199```
     200
     201#### V_MUL_U32_U24
     202
     203Opcode VOP2: 11 (0xb) for GCN 1.0/1.1; 8 (0x8) for GCN 1.2 
     204Opcode VOP3a: 267 (0x10b) for GCN 1.0/1.1; 264 (0x108) for GCN 1.2 
     205Syntax: V_MUL_U32_U24 VDST, SRC0, SRC1 
     206Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value
     207from SRC1 and store result to VDST. Any modifier doesn't affect to result. 
     208Operation: 
     209```
     210VDST = (UINT32)(SRC0&0xffffff) * (UINT32)(SRC1&0xffffff)
    110211```
    111212
     
    144245VDST = (FLOAT)SRC0 - (FLOAT)SRC1
    145246```
     247
     248#### V_SUBREV_F32
     249
     250Opcode VOP2: 5 (0x5) for GCN 1.0/1.1; 2 (0x3) for GCN 1.2 
     251Opcode VOP3a: 261 (0x105) for GCN 1.0/1.1; 259 (0x103) for GCN 1.2 
     252Syntax: V_SUBREV_F32 VDST, SRC0, SRC1 
     253Description: Subtract FP value from SRC1 and FP value from SRC0 and store result to VDST. 
     254Operation: 
     255```
     256VDST = (FLOAT)SRC1 - (FLOAT)SRC0
     257```
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