Changeset 1743 in CLRX


Ignore:
Timestamp:
Nov 22, 2015, 8:02:24 PM (5 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Doc updates: use BITCOUNT, MIN and MAX in the operation listings. Use ASFLOAT instead typecasting.

Location:
CLRadeonExtender/trunk/doc
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/doc/GcnInstrsSop1.md

    r1722 r1743  
    125125Operation: 
    126126```
    127 SDST = 0
    128 for (UINT8 i = 0; i < 32; i++)
    129     SDST += ((1U<<i) & SSRC0) == 0
     127SDST = BITCOUNT(~SSRC0)
    130128SCC = SDST!=0
    131129```
     
    139137Operation: 
    140138```
    141 SDST = 0
    142 for (UINT8 i = 0; i < 64; i++)
    143     SDST += ((1ULL<<i) & SSRC0) == 0
     139SDST = BITCOUNT(~SSRC0)
    144140SCC = SDST!=0
    145141```
     
    153149Operation: 
    154150```
    155 SDST = 0
    156 for (UINT8 i = 0; i < 32; i++)
    157     SDST += ((1U<<i) & SSRC0) != 0
     151SDST = SDST(SSRC0)
    158152SCC = SDST!=0
    159153```
     
    167161Operation: 
    168162```
    169 SDST = 0
    170 for (UINT8 i = 0; i < 64; i++)
    171     SDST += ((1ULL<<i) & SSRC0) != 0
     163SDST = BITCOUNT(SSRC0)
    172164SCC = SDST!=0
    173165```
  • CLRadeonExtender/trunk/doc/GcnInstrsSop2.md

    r1742 r1743  
    409409Operation: 
    410410```
    411 SDST = (INT32)SSRC0 > (INT32)SSRC1 ? SSRC0 : SSRC1
     411SDST = MAX((INT32)SSRC0, (INT32)SSRC1)
    412412SCC = (INT32)SSRC0 > (INT32)SSRC1
    413413```
     
    421421Operation: 
    422422```
    423 SDST = SSRC0 > SSRC1 ? SSRC0 : SSRC1
     423SDST = MAX(SSRC0, SSRC1)
    424424SCC = SSRC0 > SSRC1
    425425```
     
    433433Operation: 
    434434```
    435 SDST = (INT32)SSRC0 < (INT32)SSRC1 ? SSRC0 : SSRC1
     435SDST = MIN((INT32)SSRC0, (INT32)SSRC1)
    436436SCC = (INT32)SSRC0 < (INT32)SSRC1
    437437```
     
    445445Operation: 
    446446```
    447 SDST = SSRC0 < SSRC1 ? SSRC0 : SSRC1
     447SDST = MIN(SSRC0, SSRC1)
    448448SCC = SSRC0 < SSRC1
    449449```
  • CLRadeonExtender/trunk/doc/GcnInstrsVop2.md

    r1742 r1743  
    138138Operation: 
    139139```
    140 VDST = (FLOAT)SRC0 + (FLOAT)SRC1
     140VDST = ASFLOAT(SRC0) + ASFLOAT(SRC1)
    141141```
    142142
     
    219219Operation: 
    220220```
    221 VDST = SRC1
    222 for (UINT8 i = 0; i < 32; i++)
    223     VDST += ((1U<<i) & SRC0) != 0
     221VDST = SRC1 + BITCOUNT(SRC0)
    224222```
    225223
     
    239237
    240238Opcode VOP2: 0 (0x0) for GCN 1.0/1.1; 1 (0x0) for GCN 1.2 
    241 Opcode VOP3a: 259 (0x100) for GCN 1.0/1.1; 256 (0x100) for GCN 1.2 
     239Opcode VOP3a: 256 (0x100) for GCN 1.0/1.1; 256 (0x100) for GCN 1.2 
    242240Syntax VOP2: V_CNDMASK_B32 VDST, SRC0, SRC1, VCC 
    243241Syntax VOP3a: V_CNDMASK_B32 VDST, SRC0, SRC1, SSRC2(2) 
     
    249247```
    250248
     249#### V_CVT_PKACCUM_U8_F32
     250
     251Opcode VOP2: 44 (0x2c) for GCN 1.0/1.1 
     252Opcode VOP3a: 300 (0x12c) for GCN 1.0/1.1 
     253Syntax: V_CVT_PKACCUM_U8_F32 VDST, SRC0, SRC1 
     254Description: Convert floating point value from SRC0 to unsigned byte value with
     255rounding mode from MODE register, and store this byte to (SRC1&3)'th byte of VDST. 
     256Operation: 
     257```
     258UINT8 byte = ((SRC1&3) * 8)
     259UINT32 mask = 0xff << byte
     260UINT8 VAL8 = 0
     261FLOAT f = RNDINT(ASFLOAT(SRC0))
     262if (f > 255.0)
     263    VAL8 = 255
     264else if (f < 0.0 || f == NaN)
     265    VAL8 = 0
     266else
     267    VAL8 = f
     268VDST = (VDST&~mask) | (((UINT32)VAL8) << byte)
     269```
     270
     271#### V_CVT_PKNORM_I16_F32
     272
     273Opcode VOP2: 45 (0x2d) for GCN 1.0/1.1 
     274Opcode VOP3a: 301 (0x12d) for GCN 1.0/1.1 
     275Syntax: V_CVT_PKNORM_I16_F32 VDST, SRC0, SRC1 
     276Description: Convert normalized FP value from SRC0 and SRC1 to signed 16-bit integers with
     277rounding to nearest to even (??), and store first value to low 16-bit and
     278second to high 16-bit of the VDST. 
     279Operation: 
     280```
     281INT16 roundNorm(FLOAT S)
     282{
     283    FLOAT f = RNDNEINT(S*32767)
     284    if (f > 32767.0)
     285         return 0x7fff
     286    else if (f < -32767.0)
     287        return -0x7fff
     288    else if (f == NaN)
     289        return 0
     290    return (INT16)f
     291}
     292VDST = roundNorm(ASFLOAT(SRC0)) | ((UINT32)roundNorm(ASFLOAT(SRC1)) << 16)
     293```
     294
     295#### V_CVT_PKNORM_U16_F32
     296
     297Opcode VOP2: 46 (0x2e) for GCN 1.0/1.1 
     298Opcode VOP3a: 302 (0x12e) for GCN 1.0/1.1 
     299Syntax: V_CVT_PKNORM_U16_F32 VDST, SRC0, SRC1 
     300Description: Convert normalized FP value from SRC0 and SRC1 to unsigned 16-bit integers with
     301rounding to nearest to even (??), and store first value to low 16-bit and
     302second to high 16-bit of the VDST. 
     303Operation: 
     304```
     305UINT16 roundNorm(FLOAT S)
     306{
     307    FLOAT f = RNDNEINT(S*65535.0)
     308    INT16 VAL16 = 0
     309    if (f > 65535.0)
     310        return 0x7fff
     311    else if (f < 0.0 || f == NaN)
     312        return 0
     313    return (UINT16)f
     314}
     315VDST = roundNorm(ASFLOAT(SRC0)) | ((UINT32)roundNorm(ASFLOAT(SRC1)) << 16)
     316```
     317
     318#### V_CVT_PKRTZ_F16_F32
     319
     320Opcode VOP2: 43 (0x2f) for GCN 1.0/1.1 
     321Opcode VOP3a: 303 (0x12f) for GCN 1.0/1.1 
     322Syntax: V_CVT_PKRTZ_F16_F32 VDST, SRC0, SRC1 
     323Description: Convert normalized FP value from SRC0 and SRC1 to half floating points with
     324rounding to zero, and store first value to low 16-bit and
     325second to high 16-bit of the VDST. 
     326Operation: 
     327```
     328UINT16 D0 = ASINT16(CVT_HALF_RTZ(ASFLOAT(SRC0)))
     329UINT16 D1 = ASINT16(CVT_HALF_RTZ(ASFLOAT(SRC1)))
     330VDST = D0 | (((UINT32)D1) << 16)
     331```
     332
     333#### V_CVT_PK_U16_U32
     334
     335Opcode VOP2: 44 (0x30) for GCN 1.0/1.1 
     336Opcode VOP3a: 304 (0x130) for GCN 1.0/1.1 
     337Syntax: V_CVT_PK_U16_U32 VDST, SRC0, SRC1 
     338Description: Convert unsigned value from SRC0 and SRC1 to unsigned 16-bit values with
     339clamping, and store first value to low 16-bit and second to high 16-bit of the VDST. 
     340Operation: 
     341```
     342UINT16 D0 = MIN(SRC0, 0xffff)
     343UINT16 D1 = MIN(SRC1, 0xffff)
     344VDST = D0 | (((UINT32)D1) << 16)
     345```
     346
     347#### V_CVT_PK_I16_I32
     348
     349Opcode VOP2: 45 (0x31) for GCN 1.0/1.1 
     350Opcode VOP3a: 305 (0x131) for GCN 1.0/1.1 
     351Syntax: V_CVT_PK_I16_I32 VDST, SRC0, SRC1 
     352Description: Convert signed value from SRC0 and SRC1 to signed 16-bit values with
     353clamping, and store first value to low 16-bit and second to high 16-bit of the VDST. 
     354Operation: 
     355```
     356INT16 D0 = MAX(MIN((INT32)SRC0, 0x7fff), -0x8000)
     357INT16 D1 = MAX(MIN((INT32)SRC1, 0x7fff), -0x8000)
     358VDST = D0 | (((UINT32)D1) << 16)
     359```
     360
     361#### V_LDEXP_F32
     362
     363Opcode VOP2: 43 (0x2b) for GCN 1.0/1.1 
     364Opcode VOP3a: 299 (0x12b) for GCN 1.0/1.1 
     365Syntax: V_LDEXP_F32 VDST, SRC0, SRC1 
     366Description: Do ldexp operation on SRC0 and SRC1 (multiply SRC0 by 2**(SRC1)).
     367SRC1 is signed integer, SRC0 is floating point value. 
     368Operation: 
     369```
     370VDST = ASFLOAT(SRC0) * POW(2.0,SRC1)
     371```
     372
    251373#### V_LSHL_B32
    252374
     
    301423Operation: 
    302424```
    303 VDST = (FLOAT)SRC0 * (FLOAT)SRC1 + (FLOAT)VDST
     425VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1) + ASFLOAT(VDST)
    304426```
    305427
     
    313435Operation: 
    314436```
    315 if ((FLOAT)SRC0!=0.0 && (FLOAT)SRC1!=0.0)
    316     VDST = (FLOAT)SRC0 * (FLOAT)SRC1 + (FLOAT)VDST
     437if (ASFLOAT(SRC0)!=0.0 && ASFLOAT(SRC1)!=0.0)
     438    VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1) + ASFLOAT(VDST)
    317439```
    318440
     
    327449Operation:
    328450```
    329 VDST = (FLOAT)SRC0 * (FLOAT)FLOATLIT + (FLOAT)SRC1
     451VDST = ASFLOAT(SRC0) * ASFLOAT(FLOATLIT) + ASFLOAT(SRC1)
    330452```
    331453
     
    340462Operation:
    341463```
    342 VDST = (FLOAT)SRC0 * (FLOAT)SRC1 + (FLOAT)FLOATLIT
     464VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1) + ASFLOAT(FLOATLIT)
    343465```
    344466
     
    352474Operation: 
    353475```
    354 VDST = (FLOAT)SRC0>(FLOAT)SRC1 ? (FLOAT)SRC0 : (FLOAT)SRC1
     476VDST = MAX(ASFLOAT(SRC0), ASFLOAT(SRC1))
    355477```
    356478
     
    363485Operation: 
    364486```
    365 VDST = (INT32)SRC0>(INT32)SRC1 ? SRC0 : SRC1
     487VDST = MAX((INT32)SRC0, (INT32)SRC1)
    366488```
    367489
     
    376498Operation: 
    377499```
    378 if ((FLOAT)SRC1!=NaN)
    379     VDST = (FLOAT)SRC0>(FLOAT)SRC1 ? (FLOAT)SRC0 : (FLOAT)SRC1
     500if (ASFLOAT(SRC1)!=NaN)
     501    VDST = MAX(ASFLOAT(SRC0), ASFLOAT(SRC1))
    380502else
    381503    VDST = NaN
     
    390512Operation: 
    391513```
    392 VDST = SRC0>SRC1 ? SRC0 : SRC1
     514VDST = MAX(SRC0, SRC1)
    393515```
    394516
     
    404526```
    405527UINT32 MASK = ((1ULL << (LANEID-32)) - 1ULL) & SRC0
    406 VDST = SRC1
    407 for (UINT8 i = 0; i < 32; i++)
    408     VDST += ((1U<<i) & MASK) != 0
     528VDST = SRC1 + BITCOUNT(MASK)
    409529```
    410530
     
    420540```
    421541UINT32 MASK = ((1ULL << LANEID) - 1ULL) & SRC0
    422 VDST = SRC1
    423 for (UINT8 i = 0; i < 32; i++)
    424     VDST += ((1U<<i) & MASK) != 0
     542VDST = SRC1 + BITCOUNT(MASK)
    425543```
    426544
     
    434552Operation: 
    435553```
    436 VDST = (FLOAT)SRC0<(FLOAT)SRC1 ? (FLOAT)SRC0 : (FLOAT)SRC1
     554VDST = MIN(ASFLOAT(SRC0), ASFLOAT(SRC1))
    437555```
    438556
     
    445563Operation: 
    446564```
    447 VDST = (INT32)SRC0<(INT32)SRC1 ? SRC0 : SRC1
     565VDST = MIN((INT32)SRC0, (INT32)SRC1)
    448566```
    449567
     
    458576Operation: 
    459577```
    460 if ((FLOAT)SRC1!=NaN)
    461     VDST = (FLOAT)SRC0<(FLOAT)SRC1 ? (FLOAT)SRC0 : (FLOAT)SRC1
     578if (ASFLOAT(SRC1)!=NaN)
     579    VDST = MIN(ASFLOAT(SRC0), ASFLOAT(SRC1))
    462580else
    463581    VDST = NaN
     
    472590Operation: 
    473591```
    474 VDST = SRC0<SRC1 ? SRC0 : SRC1
     592VDST = MIN(SRC0, SRC1)
    475593```
    476594
     
    484602Operation: 
    485603```
    486 if ((FLOAT)SRC0!=0.0 && (FLOAT)SRC1!=0.0)
    487     VDST = (FLOAT)SRC0 * (FLOAT)SRC1
     604if (ASFLOAT(SRC0)!=0.0 && ASFLOAT(SRC1)!=0.0)
     605    VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1)
    488606else
    489607    VDST = 0.0
     
    498616Operation: 
    499617```
    500 VDST = (FLOAT)SRC0 * (FLOAT)SRC1
     618VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1)
    501619```
    502620
     
    587705Operation: 
    588706```
    589 VDST = (FLOAT)SRC0 - (FLOAT)SRC1
     707VDST = ASFLOAT(SRC0) - ASFLOAT(SRC1)
    590708```
    591709
     
    635753Operation: 
    636754```
    637 VDST = (FLOAT)SRC1 - (FLOAT)SRC0
     755VDST = ASFLOAT(SRC1) - ASFLOAT(SRC0)
    638756```
    639757
  • CLRadeonExtender/trunk/doc/GcnIsa.md

    r1740 r1743  
    3434* REVBIT(v) - reverse bits (n bit goes to BITS-n-1 bit,
    3535where BITS is number bits in operand).
     36* MIN(v1, v2) - return smallest value from two values
     37* MAX(v1, v2) - return largest value from two values
     38* ASHALF(v) - treat raw 16-bit integer value as IEEE half floating point value
     39* ASFLOAT(v) - treat raw 32-bit integer value as IEEE floating point value
     40* ASDOUBLE(v) - treat raw 32-bit integer value as IEEE double floating point value
     41* ASINT16(v), ASINT32(v), ASINT64(v) - treat raw floating point value as signed integer
     42* ASUINT16(v), ASUINT32(v), ASUINT64(v) - treat raw floating point value as unsigned integer
     43* RNDINT(v) - round floating point value to integer with rounding mode from MODE register,
     44    returns FP value
    3645
    3746By default, any register value is treated as unsigned integer.
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