Changeset 1746 in CLRX


Ignore:
Timestamp:
Nov 22, 2015, 9:40:13 PM (5 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Fixed and updated VOP2 instruction list.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/doc/GcnInstrsVop2.md

    r1745 r1746  
    182182Opcode: VOP3a: 283 (0x11b) for GCN 1.0/1.1; 275 (0x113) for GCN 1.2 
    183183Syntax: V_AND_B32 VDST, SRC0, SRC1 
    184 Description: Do bitwise AND on SRC0 and SRC1 and store result to VDST.
     184Description: Do bitwise AND on SRC0 and SRC1, store result to VDST.
    185185CLAMP and OMOD modifier doesn't affect on result. 
    186186Operation: 
     
    619619```
    620620
    621 #### V_MUL_HI_I32_24
     621#### V_MUL_HI_I32_I24
    622622
    623623Opcode VOP2: 10 (0xa) for GCN 1.0/1.1; 7 (0x7) for GCN 1.2 
    624624Opcode VOP3a: 266 (0x10a) for GCN 1.0/1.1; 263 (0x107) for GCN 1.2 
    625 Syntax: V_MUL_HI_I32_24 VDST, SRC0, SRC1 
     625Syntax: V_MUL_HI_I32_I24 VDST, SRC0, SRC1 
    626626Description: Multiply 24-bit signed integer value from SRC0 by 24-bit signed value from SRC1
    627627and store higher 16-bit of the result to VDST with sign extension.
     
    678678Opcode: VOP3a: 284 (0x11c) for GCN 1.0/1.1; 276 (0x114) for GCN 1.2 
    679679Syntax: V_OR_B32 VDST, SRC0, SRC1 
    680 Description: Do bitwise OR operation on SRC0 and SRC1 and store result to VDST.
     680Description: Do bitwise OR operation on SRC0 and SRC1, store result to VDST.
    681681CLAMP and OMOD modifier doesn't affect on result. 
    682682Operation: 
     
    745745```
    746746
    747 #### V_SUBREV_F32
    748 
    749 Opcode VOP2: 5 (0x5) for GCN 1.0/1.1; 2 (0x3) for GCN 1.2 
    750 Opcode VOP3a: 261 (0x105) for GCN 1.0/1.1; 259 (0x103) for GCN 1.2 
    751 Syntax: V_SUBREV_F32 VDST, SRC0, SRC1 
    752 Description: Subtract FP value of SRC0 from FP value of SRC1 and store result to VDST. 
    753 Operation: 
    754 ```
    755 VDST = ASFLOAT(SRC1) - ASFLOAT(SRC0)
    756 ```
    757 
    758747#### V_SUBBREV_U32
    759748
     
    775764```
    776765
     766#### V_SUBREV_F32
     767
     768Opcode VOP2: 5 (0x5) for GCN 1.0/1.1; 2 (0x3) for GCN 1.2 
     769Opcode VOP3a: 261 (0x105) for GCN 1.0/1.1; 259 (0x103) for GCN 1.2 
     770Syntax: V_SUBREV_F32 VDST, SRC0, SRC1 
     771Description: Subtract FP value of SRC0 from FP value of SRC1 and store result to VDST. 
     772Operation: 
     773```
     774VDST = ASFLOAT(SRC1) - ASFLOAT(SRC0)
     775```
     776
    777777#### V_SUBREV_I32, V_SUBREV_U32
    778778
     
    797797Opcode: VOP2: 29 (0x1d) for GCN 1.0/1.1; 21 (0x15) for GCN 1.2 
    798798Opcode: VOP3a: 285 (0x11d) for GCN 1.0/1.1; 277 (0x115) for GCN 1.2 
    799 Syntax: V_OR_B32 VDST, SRC0, SRC1 
    800 Description: Do bitwise XOR operation on SRC0 and SRC1 and store result to VDST.
     799Syntax: V_XOR_B32 VDST, SRC0, SRC1 
     800Description: Do bitwise XOR operation on SRC0 and SRC1, store result to VDST.
    801801CLAMP and OMOD modifier doesn't affect on result. 
    802802Operation: 
Note: See TracChangeset for help on using the changeset viewer.