Changeset 1752 in CLRX


Ignore:
Timestamp:
Nov 26, 2015, 8:51:00 PM (5 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Updated VOP1 instruction's list.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/doc/GcnInstrsVop1.md

    r1751 r1752  
    227227Alphabetically sorted instruction list:
    228228
     229#### V_CVT_F32_I32
     230
     231Opcode VOP2: 5 (0x5) 
     232Opcode VOP3A: 389 (0x185) for GCN 1.0/1.1; 325 (0x145) for GCN 1.2 
     233Syntax: V_CVT_F32_I32 VDST, SRC0 
     234Description: Convert signed 32-bit integer to single FP value, and store it to VDST. 
     235Operation: 
     236```
     237VDST = (FLOAT)(INT32)SRC0
     238```
     239
     240#### V_CVT_F32_U32
     241
     242Opcode VOP2: 6 (0x6) 
     243Opcode VOP3A: 390 (0x186) for GCN 1.0/1.1; 326 (0x146) for GCN 1.2 
     244Syntax: V_CVT_F32_U32 VDST, SRC0 
     245Description: Convert unsigned 32-bit integer to single FP value, and store it to VDST. 
     246Operation: 
     247```
     248VDST = (FLOAT)SRC0
     249
     250#### V_CVT_F64_I32
     251
     252Opcode VOP2: 4 (0x4) 
     253Opcode VOP3A: 388 (0x184) for GCN 1.0/1.1; 324 (0x144) for GCN 1.2 
     254Syntax: V_CVT_F64_I32 VDST(2), SRC0 
     255Description: Convert signed 32-bit integer to double FP value, and store it to VDST. 
     256Operation: 
     257```
     258VDST = (DOUBLE)(INT32)SRC0
     259```
     260
     261#### V_CVT_I32_F32
     262
     263Opcode VOP2: 8 (0x8) 
     264Opcode VOP3A: 392 (0x188) for GCN 1.0/1.1; 328 (0x148) for GCN 1.2 
     265Syntax: V_CVT_I32_F32 VDST, SRC0 
     266Description: Convert 32-bit floating point value from SRC0 to signed 32-bit integer, and
     267store result to VDST. Conversion uses rounding to zero. If value is higher/lower than
     268maximal/minimal integer then store MAX_INT32/MIN_INT32 to VDST.
     269If input value is NaN then store 0 to VDST. 
     270Operation: 
     271```
     272VDST = 0
     273if (SRC0!=NAN)
     274    VDST = (INT32)MAX(MIN(RNDTZINT(ASFLOAT(SRC0)), 2147483647.0), -2147483648.0)
     275```
     276
     277#### V_CVT_I32_F64
     278
     279Opcode VOP2: 3 (0x3) 
     280Opcode VOP3A: 387 (0x183) for GCN 1.0/1.1; 323 (0x143) for GCN 1.2 
     281Syntax: V_CVT_I32_F64 VDST, SRC0(2) 
     282Description: Convert 64-bit floating point value from SRC0 to signed 32-bit integer, and
     283store result to VDST. Conversion uses rounding to zero. If value is higher/lower than
     284maximal/minimal integer then store MAX_INT32/MIN_INT32 to VDST.
     285If input value is NaN then store 0 to VDST. 
     286Operation: 
     287```
     288VDST = 0
     289if (SRC0!=NAN)
     290    VDST = (INT32)MAX(MIN(RNDTZINT(ASDOUBLE(SRC0)), 2147483647.0), -2147483648.0)
     291```
     292
     293#### V_CVT_U32_F32
     294
     295Opcode VOP2: 7 (0x7) 
     296Opcode VOP3A: 391 (0x187) for GCN 1.0/1.1; 327 (0x147) for GCN 1.2 
     297Syntax: V_CVT_U32_F32 VDST, SRC0 
     298Description: Convert 32-bit floating point value from SRC0 to unsigned 32-bit integer, and
     299store result to VDST. Conversion uses rounding to zero. If value is higher than
     300maximal integer then store MAX_UINT32 to VDST.
     301If input value is NaN then store 0 to VDST. 
     302Operation: 
     303```
     304VDST = 0
     305if (SRC0!=NAN)
     306    VDST = (UINT32)MIN(RNDTZINT(ASFLOAT(SRC0)), 4294967295.0)
     307```
     308
     309#### V_MOV_B32
     310
     311Opcode VOP2: 1 (0x1) 
     312Opcode VOP3A: 385 (0x181) for GCN 1.0/1.1; 321 (0x141) for GCN 1.2 
     313Syntax: V_MOV_B32 VDST, SRC0 
     314Description: Move SRC0 into VDST. 
     315Operation: 
     316```
     317VDST = SRC0
     318```
     319
    229320#### V_NOP
    230321
     322Opcode VOP2: 0 (0x0) 
     323Opcode VOP3A: 384 (0x180) for GCN 1.0/1.1; 320 (0x140) for GCN 1.2 
     324Syntax: V_NOP 
     325Description: Do nothing.
     326
     327#### V_READFIRSTLANE_B32
     328
     329Opcode VOP2: 2 (0x2) 
     330Opcode VOP3A: 386 (0x182) for GCN 1.0/1.1; 322 (0x142) for GCN 1.2 
     331Syntax: V_READFIRSTLANE_B32 SDST, VSRC0 
     332Description: Copy one VSRC0 lane value to one SDST. Lane (thread id) is first active lane id or
     333first lane id all lanes are inactive. SSRC1 can be SGPR or M0. Ignores EXEC mask. 
     334Operation: 
     335Operation: 
     336```
     337UINT8 firstlane = 0
     338for (UINT8 i = 0; i < 64; i++)
     339    if ((1ULL<<i) & EXEC) != 0)
     340    { firstlane = i; break; }
     341SDST = VSRC0[firstlane]
     342```
Note: See TracChangeset for help on using the changeset viewer.