Changeset 1754 in CLRX


Ignore:
Timestamp:
Nov 27, 2015, 10:48:06 PM (4 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Updated VOP1 instruction list.

File:
1 edited

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  • CLRadeonExtender/trunk/doc/GcnInstrsVop1.md

    r1752 r1754  
    227227Alphabetically sorted instruction list:
    228228
     229#### V_CVT_F16_F32
     230
     231Opcode VOP2: 10 (0xa) 
     232Opcode VOP3A: 394 (0x18a) for GCN 1.0/1.1; 330 (0x14a) for GCN 1.2 
     233Syntax: V_CVT_F16_F32 VDST, SRC0 
     234Description: Convert single FP value to half floating point value with rounding from
     235MODE register (single FP rounding mode), and store result to VDST.
     236If absolute value is too high, then store -/+infinity to VDST. 
     237Operation: 
     238```
     239VDST = RNDHALF(ASFLOAT(SRC0))
     240```
     241
     242#### V_CVT_F32_F16
     243
     244Opcode VOP2: 11 (0xb) 
     245Opcode VOP3A: 395 (0x18b) for GCN 1.0/1.1; 331 (0x14b) for GCN 1.2 
     246Syntax: V_CVT_F32_F16 VDST, SRC0 
     247Description: Convert half FP value to single FP value, and store result to VDST. 
     248Operation: 
     249```
     250VDST = (FLOAT)(ASHALF(SRC0))
     251```
     252
    229253#### V_CVT_F32_I32
    230254
     
    307331```
    308332
     333#### V_MOV_FED_B32
     334
     335Opcode VOP2: 9 (0x9) 
     336Opcode VOP3A: 393 (0x189) for GCN 1.0/1.1; 329 (0x149) for GCN 1.2 
     337Syntax: V_MOV_FED_B32 VDST, SRC0 
     338Description: Introduce edc double error upon write to dest vgpr without causing an exception
     339(???).
     340
    309341#### V_MOV_B32
    310342
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