Changeset 1755 in CLRX


Ignore:
Timestamp:
Nov 27, 2015, 11:46:36 PM (4 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Updated VOP1 instruction list: added V_CVT_RPI_I32_F32 and V_CVT_FLR_I32_F32.

File:
1 edited

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  • CLRadeonExtender/trunk/doc/GcnInstrsVop1.md

    r1754 r1755  
    283283```
    284284
     285#### V_CVT_FLR_I32_F32
     286
     287Opcode VOP2: 13 (0xd) 
     288Opcode VOP3A: 397 (0x18d) for GCN 1.0/1.1; 333 (0x14d) for GCN 1.2 
     289Syntax: V_CVT_FLR_I32_F32 VDST, SRC0 
     290Description: Convert 32-bit floating point value from SRC0 to signed 32-bit integer, and
     291store result to VDST. Conversion uses rounding to negative infinity (floor).
     292If value is higher/lower than maximal/minimal integer then store MAX_INT32/MIN_INT32 to VDST.
     293If input value is NaN/-NaN then store MAX_INT32/MIN_INT32 to VDST. 
     294Operation: 
     295```
     296if (ABS(SRC0)!=NAN)
     297    VDST = (INT32)MAX(MIN(FLOOR(ASFLOAT(SRC0)), 2147483647.0), -2147483648.0)
     298else
     299    VDST = (INT32)SRC0>=0 ? 2147483647 : -2147483648
     300```
     301
    285302#### V_CVT_I32_F32
    286303
     
    315332```
    316333
     334#### V_CVT_RPI_I32_F32
     335
     336Opcode VOP2: 12 (0xc) 
     337Opcode VOP3A: 396 (0x18c) for GCN 1.0/1.1; 332 (0x14c) for GCN 1.2 
     338Syntax: V_CVT_RPI_I32_F32 VDST, SRC0 
     339Description: Convert 32-bit floating point value from SRC0 to signed 32-bit integer, and
     340store result to VDST. Conversion adds 0.5 to value and rounds negative infinity (floor).
     341If value is higher/lower than maximal/minimal integer then store MAX_INT32/MIN_INT32 to VDST.
     342If input value is NaN/-NaN then store MAX_INT32/MIN_INT32 to VDST. 
     343Description: 
     344```
     345if (ABS(SRC0)!=NAN)
     346    VDST = (INT32)MAX(MIN(FLOOR(ASFLOAT(SRC0) + 0.5), 2147483647.0), -2147483648.0)
     347else
     348    VDST = (INT32)SRC0>=0 ? 2147483647 : -2147483648
     349```
     350
    317351#### V_CVT_U32_F32
    318352
     
    362396Opcode VOP3A: 386 (0x182) for GCN 1.0/1.1; 322 (0x142) for GCN 1.2 
    363397Syntax: V_READFIRSTLANE_B32 SDST, VSRC0 
    364 Description: Copy one VSRC0 lane value to one SDST. Lane (thread id) is first active lane id or
    365 first lane id all lanes are inactive. SSRC1 can be SGPR or M0. Ignores EXEC mask. 
     398Description: Copy one VSRC0 lane value to one SDST. Lane (thread id) is first active lane id
     399or first lane id all lanes are inactive. SSRC1 can be SGPR or M0. Ignores EXEC mask. 
    366400Operation: 
    367401Operation: 
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