Changeset 1758 in CLRX


Ignore:
Timestamp:
Nov 28, 2015, 2:42:18 PM (4 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Updated VOP1 instruction list (added new instructions).

File:
1 edited

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  • CLRadeonExtender/trunk/doc/GcnInstrsVop1.md

    r1757 r1758  
    237237Operation: 
    238238```
    239 VDST = RNDHALF(ASFLOAT(SRC0))
     239VDST = CVTHALF(ASFLOAT(SRC0))
    240240```
    241241
     
    251251```
    252252
     253#### V_CVT_F32_F64
     254
     255Opcode VOP2: 15 (0xf) 
     256Opcode VOP3A: 399 (0x18f) for GCN 1.0/1.1; 335 (0x14f) for GCN 1.2 
     257Syntax: V_CVT_F32_F64 VDST, SRC0(2) 
     258Description: Convert double FP value to single floating point value with rounding from
     259MODE register (single FP rounding mode), and store result to VDST.
     260If absolute value is too high, then store -/+infinity to VDST. 
     261Operation: 
     262```
     263VDST = CVTHALF(ASDOUBLE(SRC0))
     264```
     265
    253266#### V_CVT_F32_I32
    254267
     
    271284```
    272285VDST = (FLOAT)SRC0
     286```
     287
     288#### V_CVT_F32_UBYTE0
     289
     290Opcode VOP2: 17 (0x11) 
     291Opcode VOP3A: 401 (0x191) for GCN 1.0/1.1; 337 (0x151) for GCN 1.2 
     292Syntax: V_CVT_F32_UBYTE0 VDST, SRC0 
     293Description: Convert the first unsigned 8-bit byte from SRC0 to single FP value,
     294and store it to VDST. 
     295Operation: 
     296```
     297VDST = (FLOAT)(SRC0 & 0xff)
     298```
     299
     300#### V_CVT_F32_UBYTE1
     301
     302Opcode VOP2: 18 (0x12) 
     303Opcode VOP3A: 402 (0x192) for GCN 1.0/1.1; 338 (0x152) for GCN 1.2 
     304Syntax: V_CVT_F32_UBYTE1 VDST, SRC0 
     305Description: Convert the second unsigned 8-bit byte from SRC0 to single FP value,
     306and store it to VDST. 
     307Operation: 
     308```
     309VDST = (FLOAT)((SRC0>>8) & 0xff)
     310```
     311
     312#### V_CVT_F32_UBYTE2
     313
     314Opcode VOP2: 19 (0x13) 
     315Opcode VOP3A: 403 (0x193) for GCN 1.0/1.1; 339 (0x153) for GCN 1.2 
     316Syntax: V_CVT_F32_UBYTE2 VDST, SRC0 
     317Description: Convert the third unsigned 8-bit byte from SRC0 to single FP value,
     318and store it to VDST. 
     319Operation: 
     320```
     321VDST = (FLOAT)((SRC0>>16) & 0xff)
     322```
     323
     324#### V_CVT_F32_UBYTE3
     325
     326Opcode VOP2: 20 (0x14) 
     327Opcode VOP3A: 404 (0x194) for GCN 1.0/1.1; 340 (0x154) for GCN 1.2 
     328Syntax: V_CVT_F32_UBYTE3 VDST, SRC0 
     329Description: Convert the fourth unsigned 8-bit byte from SRC0 to single FP value,
     330and store it to VDST. 
     331Operation: 
     332```
     333VDST = (FLOAT)(SRC0>>24)
     334```
     335
     336#### V_CVT_F64_F32
     337
     338Opcode VOP2: 16 (0x10) 
     339Opcode VOP3A: 400 (0x190) for GCN 1.0/1.1; 336 (0x150) for GCN 1.2 
     340Syntax: V_CVT_F64_F32 VDST(2), SRC0 
     341Description: Convert single FP value to double FP value, and store result to VDST. 
     342Operation: 
     343```
     344VDST = (DOUBLE)(ASFLOAT(SRC0))
    273345```
    274346
     
    331403if (SRC0!=NAN)
    332404    VDST = (INT32)MAX(MIN(RNDTZINT(ASDOUBLE(SRC0)), 2147483647.0), -2147483648.0)
     405```
     406
     407#### V_CVT_OFF_F32_I4
     408
     409Opcode VOP2: 14 (0xe) 
     410Opcode VOP3A: 398 (0x18e) for GCN 1.0/1.1; 334 (0x14e) for GCN 1.2 
     411Syntax: V_CVT_OFF_F32_I4 VDST, SRC0 
     412Description: Convert 4-bit signed value from SRC0 to floating point value, normalize that
     413value to range -0.5:0.4375 and store result to VDST. 
     414Operation: 
     415```
     416VDST = (FLOAT)((SRC0 & 0xf) ^ 8) / 16.0 - 0.5
    333417```
    334418
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