Changeset 1767 in CLRX


Ignore:
Timestamp:
Nov 29, 2015, 8:27:08 PM (4 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Doc updates: Fixes in VOP1instruction list.

File:
1 edited

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  • CLRadeonExtender/trunk/doc/GcnInstrsVop1.md

    r1766 r1767  
    563563```
    564564
     565#### V_FFBH_I32
     566
     567Opcode VOP1: 59 (0x3b) for GCN 1.0/1.1; 47 (0x2f) for GCN 1.2 
     568Opcode VOP3A: 443 (0x1bb) for GCN 1.0/1.1; 367 (0x16f) for GCN 1.2 
     569Syntax: V_FFBH_I32 VDST, SRC0 
     570Description: Find last opposite bit to sign in SRC0. If found, store number of skipped bits
     571to VDST, otherwise set VDST to -1. 
     572Operation: 
     573```
     574VDST = -1
     575UINT32 bitval = (INT32)SRC0>=0 ? 1 : 0
     576for (INT8 i = 31; i >= 0; i--)
     577    if ((1U<<i) & SRC0) == (bitval<<i))
     578    { VDST = 31-i; break; }
     579```
     580
    565581#### V_FFBL_B32
    566582
     
    576592    if ((1U<<i) & SRC0) != 0)
    577593    { VDST = i; break; }
    578 ```
    579 
    580 #### V_FFBH_I32
    581 
    582 Opcode VOP1: 59 (0x3b) for GCN 1.0/1.1; 47 (0x2f) for GCN 1.2 
    583 Opcode VOP3A: 443 (0x1bb) for GCN 1.0/1.1; 367 (0x16f) for GCN 1.2 
    584 Syntax: V_FFBH_I32 VDST, SRC0 
    585 Description: Find last opposite bit to sign in SRC0. If found, store number of skipped bits
    586 to VDST, otherwise set VDST to -1. 
    587 Operation: 
    588 ```
    589 VDST = -1
    590 UINT32 bitval = (INT32)SRC0>=0 ? 1 : 0
    591 for (INT8 i = 31; i >= 0; i--)
    592     if ((1U<<i) & SRC0) == (bitval<<i))
    593     { VDST = 31-i; break; }
    594594```
    595595
     
    625625#### V_FRACT_F64
    626626
    627 Opcode VOP1: 62 (0x3e) for GCN 1.0/1.1; 51 (0x33) for GCN 1.2 
    628 Opcode VOP3A: 446 (0x1be) for GCN 1.0/1.1; 371 (0x173) for GCN 1.2 
     627Opcode VOP1: 62 (0x3e) for GCN 1.0/1.1; 52 (0x32) for GCN 1.2 
     628Opcode VOP3A: 446 (0x1be) for GCN 1.0/1.1; 372 (0x172) for GCN 1.2 
    629629Syntax: V_FRACT_F64 VDST(2), SRC0(2) 
    630630Description: Get fractional from double floating point value SRC0 and store it to VDST.
     
    737737
    738738Opcode VOP1: 39 (0x27) for GCN 1.0/1.1; 33 (0x21) for GCN 1.2 
    739 Opcode VOP3A: 422 (0x1a6) for GCN 1.0/1.1; 353 (0x161) for GCN 1.2 
     739Opcode VOP3A: 423 (0x1a7) for GCN 1.0/1.1; 353 (0x161) for GCN 1.2 
    740740Syntax: V_LOG_F32 VDST, SRC0 
    741741Description: Approximate logarithm of base 2 from floating point value SRC0, and store result
     
    753753```
    754754
     755#### V_MOV_B32
     756
     757Opcode VOP1: 1 (0x1) 
     758Opcode VOP3A: 385 (0x181) for GCN 1.0/1.1; 321 (0x141) for GCN 1.2 
     759Syntax: V_MOV_B32 VDST, SRC0 
     760Description: Move SRC0 into VDST. 
     761Operation: 
     762```
     763VDST = SRC0
     764```
     765
    755766#### V_MOV_FED_B32
    756767
     
    761772(???).
    762773
    763 #### V_MOV_B32
    764 
    765 Opcode VOP1: 1 (0x1) 
    766 Opcode VOP3A: 385 (0x181) for GCN 1.0/1.1; 321 (0x141) for GCN 1.2 
    767 Syntax: V_MOV_B32 VDST, SRC0 
    768 Description: Move SRC0 into VDST. 
    769 Operation: 
    770 ```
    771 VDST = SRC0
    772 ```
    773 
    774774#### V_MOVRELD_B32
    775775
    776 Opcode VOP1: 66 (0x42) for GCN 1.0/1.1; 54 (0x35) for GCN 1.2 
    777 Opcode VOP3A: 450 (0x1c2) for GCN 1.0/1.1; 374 (0x175) for GCN 1.2 
     776Opcode VOP1: 66 (0x42) for GCN 1.0/1.1; 54 (0x34) for GCN 1.2 
     777Opcode VOP3A: 450 (0x1c2) for GCN 1.0/1.1; 374 (0x174) for GCN 1.2 
    778778Syntax: V_MOVRELD VDST, VSRC0 
    779779Description: Move SRC0 to VGPR[VDST_NUMBER+M0]. 
     
    785785#### V_MOVRELS_B32
    786786
    787 Opcode VOP1: 67 (0x43) for GCN 1.0/1.1; 55 (0x36) for GCN 1.2 
    788 Opcode VOP3A: 451 (0x1c3) for GCN 1.0/1.1; 375 (0x176) for GCN 1.2 
     787Opcode VOP1: 67 (0x43) for GCN 1.0/1.1; 55 (0x35) for GCN 1.2 
     788Opcode VOP3A: 451 (0x1c3) for GCN 1.0/1.1; 375 (0x175) for GCN 1.2 
    789789Syntax: V_MOVRELS VDST, VSRC0 
    790790Description: Move SRC0[SRC0_NUMBER+M0] to VDST. 
     
    796796#### V_MOVRELSD_B32
    797797
    798 Opcode VOP1: 67 (0x43) for GCN 1.0/1.1; 55 (0x36) for GCN 1.2 
    799 Opcode VOP3A: 451 (0x1c3) for GCN 1.0/1.1; 375 (0x176) for GCN 1.2 
     798Opcode VOP1: 68 (0x44) for GCN 1.0/1.1; 56 (0x36) for GCN 1.2 
     799Opcode VOP3A: 452 (0x1c4) for GCN 1.0/1.1; 376 (0x176) for GCN 1.2 
    800800Syntax: V_MOVRELSD VDST, VSRC0 
    801801Description: Move SRC0[SRC0_NUMBER+M0] to VGPR[VDST_NUMBER+M0]. 
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