Changeset 1772 in CLRX


Ignore:
Timestamp:
Dec 2, 2015, 11:49:55 PM (4 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Updated docs (OMOD and CLAMP notes).

Location:
CLRadeonExtender/trunk/doc
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/doc/GcnInstrsVop1.md

    r1771 r1772  
    5757
    5858NOTE: OMOD modifier doesn't work if output denormals are allowed
    59 (5 bit of MODE register for single precision or 7 bit for double precision).
     59(5 bit of MODE register for single precision or 7 bit for double precision). 
     60NOTE: OMOD and CLAMP modifier affects only for instruction that output is
     61floating point value.
    6062
    6163Negation and absolute value can be combined: `-ABS(V0)`. Modifiers CLAMP and
  • CLRadeonExtender/trunk/doc/GcnInstrsVop2.md

    r1771 r1772  
    5858
    5959NOTE: OMOD modifier doesn't work if output denormals are allowed
    60 (5 bit of MODE register for single precision or 7 bit for double precision).
     60(5 bit of MODE register for single precision or 7 bit for double precision). 
     61NOTE: OMOD and CLAMP modifier affects only for instruction that output is
     62floating point value.
    6163
    6264Negation and absolute value can be combined: `-ABS(V0)`. Modifiers CLAMP and
     
    185187Opcode: VOP3A: 283 (0x11b) for GCN 1.0/1.1; 275 (0x113) for GCN 1.2 
    186188Syntax: V_AND_B32 VDST, SRC0, SRC1 
    187 Description: Do bitwise AND on SRC0 and SRC1, store result to VDST.
    188 CLAMP and OMOD modifier doesn't affect on result. 
     189Description: Do bitwise AND on SRC0 and SRC1, store result to VDST. 
    189190Operation: 
    190191```
     
    244245Syntax VOP3A: V_CNDMASK_B32 VDST, SRC0, SRC1, SSRC2(2) 
    245246Description: If bit for current lane of VCC or SDST is set then store SRC1 to VDST,
    246 otherwise store SRC0 to VDST. CLAMP and OMOD modifier doesn't affect on result.
     247otherwise store SRC0 to VDST.
    247248Operation: 
    248249```
     
    633634Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value
    634635from SRC1 and store higher 16-bit of the result to VDST.
    635 Any modifier doesn't affect to result. 
     636Any modifier doesn't affect on result. 
    636637Operation: 
    637638```
     
    645646Syntax: V_MUL_I32_I24 VDST, SRC0, SRC1 
    646647Description: Multiply 24-bit signed integer value from SRC0 by 24-bit signed value from SRC1
    647 and store result to VDST. Any modifier doesn't affect to result. 
     648and store result to VDST. Any modifier doesn't affect on result. 
    648649Operation: 
    649650```
     
    659660Syntax: V_MUL_U32_U24 VDST, SRC0, SRC1 
    660661Description: Multiply 24-bit unsigned integer value from SRC0 by 24-bit unsigned value
    661 from SRC1 and store result to VDST. Any modifier doesn't affect to result. 
     662from SRC1 and store result to VDST. Any modifier doesn't affect on result. 
    662663Operation: 
    663664```
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