Changeset 1773 in CLRX


Ignore:
Timestamp:
Dec 3, 2015, 7:48:42 PM (4 years ago)
Author:
matszpk
Message:

CLRadeonExtender: Doc updates: Reorder VOP2 list. Added info about NEG and ABS modifier.

Location:
CLRadeonExtender/trunk/doc
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/doc/GcnInstrsVop1.md

    r1772 r1773  
    5959(5 bit of MODE register for single precision or 7 bit for double precision). 
    6060NOTE: OMOD and CLAMP modifier affects only for instruction that output is
    61 floating point value.
     61floating point value. 
     62NOTE: ABS and negation is applied to source operand for any instruction.
    6263
    6364Negation and absolute value can be combined: `-ABS(V0)`. Modifiers CLAMP and
  • CLRadeonExtender/trunk/doc/GcnInstrsVop2.md

    r1772 r1773  
    6060(5 bit of MODE register for single precision or 7 bit for double precision). 
    6161NOTE: OMOD and CLAMP modifier affects only for instruction that output is
    62 floating point value.
     62floating point value. 
     63NOTE: ABS and negation is applied to source operand for any instruction.
    6364
    6465Negation and absolute value can be combined: `-ABS(V0)`. Modifiers CLAMP and
     
    251252```
    252253
     254#### V_CVT_PK_I16_I32
     255
     256Opcode VOP2: 49 (0x31) for GCN 1.0/1.1 
     257Opcode VOP3A: 305 (0x131) for GCN 1.0/1.1 
     258Syntax: V_CVT_PK_I16_I32 VDST, SRC0, SRC1 
     259Description: Convert signed value from SRC0 and SRC1 to signed 16-bit values with
     260clamping, and store first value to low 16-bit and second to high 16-bit of the VDST. 
     261Operation: 
     262```
     263INT16 D0 = MAX(MIN((INT32)SRC0, 0x7fff), -0x8000)
     264INT16 D1 = MAX(MIN((INT32)SRC1, 0x7fff), -0x8000)
     265VDST = D0 | (((UINT32)D1) << 16)
     266```
     267
     268#### V_CVT_PK_U16_U32
     269
     270Opcode VOP2: 48 (0x30) for GCN 1.0/1.1 
     271Opcode VOP3A: 304 (0x130) for GCN 1.0/1.1 
     272Syntax: V_CVT_PK_U16_U32 VDST, SRC0, SRC1 
     273Description: Convert unsigned value from SRC0 and SRC1 to unsigned 16-bit values with
     274clamping, and store first value to low 16-bit and second to high 16-bit of the VDST. 
     275Operation: 
     276```
     277UINT16 D0 = MIN(SRC0, 0xffff)
     278UINT16 D1 = MIN(SRC1, 0xffff)
     279VDST = D0 | (((UINT32)D1) << 16)
     280```
     281
    253282#### V_CVT_PKACCUM_U8_F32
    254283
     
    324353```
    325354
    326 #### V_CVT_PK_U16_U32
    327 
    328 Opcode VOP2: 48 (0x30) for GCN 1.0/1.1 
    329 Opcode VOP3A: 304 (0x130) for GCN 1.0/1.1 
    330 Syntax: V_CVT_PK_U16_U32 VDST, SRC0, SRC1 
    331 Description: Convert unsigned value from SRC0 and SRC1 to unsigned 16-bit values with
    332 clamping, and store first value to low 16-bit and second to high 16-bit of the VDST. 
    333 Operation: 
    334 ```
    335 UINT16 D0 = MIN(SRC0, 0xffff)
    336 UINT16 D1 = MIN(SRC1, 0xffff)
    337 VDST = D0 | (((UINT32)D1) << 16)
    338 ```
    339 
    340 #### V_CVT_PK_I16_I32
    341 
    342 Opcode VOP2: 49 (0x31) for GCN 1.0/1.1 
    343 Opcode VOP3A: 305 (0x131) for GCN 1.0/1.1 
    344 Syntax: V_CVT_PK_I16_I32 VDST, SRC0, SRC1 
    345 Description: Convert signed value from SRC0 and SRC1 to signed 16-bit values with
    346 clamping, and store first value to low 16-bit and second to high 16-bit of the VDST. 
    347 Operation: 
    348 ```
    349 INT16 D0 = MAX(MIN((INT32)SRC0, 0x7fff), -0x8000)
    350 INT16 D1 = MAX(MIN((INT32)SRC1, 0x7fff), -0x8000)
    351 VDST = D0 | (((UINT32)D1) << 16)
    352 ```
    353 
    354355#### V_LDEXP_F32
    355356
Note: See TracChangeset for help on using the changeset viewer.