Changeset 3073 in CLRX


Ignore:
Timestamp:
May 22, 2017, 8:39:10 PM (2 years ago)
Author:
matszpk
Message:

CLRadeonExtender: GCNDisasm: Add new MIMG instructions and encoding changes (for AMD VEGA).

Location:
CLRadeonExtender/trunk
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/amdasm/GCNDisasm.cpp

    r3070 r3073  
    24022402         uint32_t insnCode2)
    24032403{
     2404    const bool isGCN14 = ((arch&ARCH_RXVEGA)!=0);
    24042405    FastOutputBuffer& output = dasm.output;
    24052406    char* bufStart = output.reserve(150);
     
    24242425    *bufPtr++ = ',';
    24252426    *bufPtr++ = ' ';
    2426     decodeGCNOperandNoLit(dasm, ((insnCode2>>14)&0x7c), (insnCode & 0x8000)?4:8,
    2427                           bufPtr, arch);
     2427    decodeGCNOperandNoLit(dasm, ((insnCode2>>14)&0x7c),
     2428                (((insnCode & 0x8000)!=0) && !isGCN14) ? 4: 8, bufPtr, arch);
    24282429   
    24292430    const cxuint ssamp = (insnCode2>>21)&0x1f;
     
    24532454        putChars(bufPtr, " slc", 4);
    24542455    if (insnCode & 0x8000)
    2455         putChars(bufPtr, " r128", 5);
     2456    {
     2457        if (!isGCN14)
     2458            putChars(bufPtr, " r128", 5);
     2459        else
     2460            putChars(bufPtr, " a16", 4);
     2461    }
    24562462    if (insnCode & 0x10000)
    24572463        putChars(bufPtr, " tfe", 4);
  • CLRadeonExtender/trunk/amdasm/GCNInstructions.cpp

    r3072 r3073  
    23752375    { "image_gather4",       GCNENC_MIMG,   GCN_MIMG_GATHER|GCN_MLOAD, 64,   ARCH_GCN_ALL  },
    23762376    { "image_gather4_cl",    GCNENC_MIMG,   GCN_MIMG_VAGE2|GCN_MIMG_GATHER|GCN_MLOAD, 65,   ARCH_GCN_ALL  },
     2377    { "image_gather4h",      GCNENC_MIMG,   GCN_MIMG_VAGE2|GCN_MIMG_GATHER|GCN_MLOAD, 66,   ARCH_RXVEGA  },
    23772378    { "image_gather4_l",     GCNENC_MIMG,   GCN_MIMG_VAGE2|GCN_MIMG_GATHER|GCN_MLOAD, 68,   ARCH_GCN_ALL  },
    23782379    { "image_gather4_b",     GCNENC_MIMG,   GCN_MIMG_VAGE2|GCN_MIMG_GATHER|GCN_MLOAD, 69,   ARCH_GCN_ALL  },
     
    23812382    { "image_gather4_c",     GCNENC_MIMG,   GCN_MIMG_VAGE2|GCN_MIMG_GATHER|GCN_MLOAD, 72,   ARCH_GCN_ALL  },
    23822383    { "image_gather4_c_cl",  GCNENC_MIMG,   GCN_MIMG_VAGE3|GCN_MIMG_GATHER|GCN_MLOAD, 73,   ARCH_GCN_ALL  },
     2384    { "image_gather4h_pck",  GCNENC_MIMG,   GCN_MIMG_VAGE2|GCN_MIMG_GATHER|GCN_MLOAD, 74,   ARCH_RXVEGA  },
     2385    { "image_gather8h_pck",  GCNENC_MIMG,   GCN_MIMG_VAGE2|GCN_MIMG_GATHER|GCN_MLOAD, 75,   ARCH_RXVEGA  },
    23832386    { "image_gather4_c_l",   GCNENC_MIMG,   GCN_MIMG_VAGE3|GCN_MIMG_GATHER|GCN_MLOAD, 76,   ARCH_GCN_ALL  },
    23842387    { "image_gather4_c_b",   GCNENC_MIMG,   GCN_MIMG_VAGE3|GCN_MIMG_GATHER|GCN_MLOAD, 77,   ARCH_GCN_ALL  },
  • CLRadeonExtender/trunk/tests/amdasm/GCNDisasmOpc14.cpp

    r3072 r3073  
    469469    { 0xe09f725bU, 0x23343d12U, true, "        buffer_store_format_d16_hi_x "
    470470        "v61, v[18:19], s[80:83], s35 offen idxen offset:603 glc slc lds\n" },
     471    /* MIMG instructions */
     472    /* TODO: check register ranges */
     473    { 0xf108fb00U, 0x00159d79U, true, "        image_gather4h  "
     474            "v[157:160], v[121:124], s[84:91], s[0:3] dmask:11 unorm glc a16 da\n" },
     475    { 0xf1087b00U, 0x00159d79U, true, "        image_gather4h  "
     476            "v[157:160], v[121:124], s[84:91], s[0:3] dmask:11 unorm glc da\n" },
     477    { 0xf128fb00U, 0x00159d79U, true, "        image_gather4h_pck "
     478            "v[157:160], v[121:124], s[84:91], s[0:3] dmask:11 unorm glc a16 da\n" },
     479    { 0xf12cfb00U, 0x00159d79U, true, "        image_gather8h_pck "
     480            "v[157:160], v[121:124], s[84:91], s[0:3] dmask:11 unorm glc a16 da\n" },
    471481    { 0, 0, false, nullptr }
    472482};
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