Changeset 3080 in CLRX


Ignore:
Timestamp:
May 27, 2017, 12:03:49 PM (2 years ago)
Author:
matszpk
Message:

CLRadeonExtender: GCNAsm: Add testcases for checking new SOPx instructions (AMD VEGA arch).

File:
1 edited

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Unmodified
Added
Removed
  • CLRadeonExtender/trunk/tests/amdasm/GCNAsmOpc14.cpp

    r3077 r3080  
    2323const GCNAsmOpcodeCase encGCN14OpcodeCases[] =
    2424{
     25    /* extra scalar registers */
    2526    { "s_add_u32 s21, shared_base, s61\n", 0x80153debU, 0, false, true, "" },
    2627    { "s_add_u32 s21, src_shared_base, s61\n", 0x80153debU, 0, false, true, "" },
     
    5556    { "    s_add_u32  tba_lo, s4, s61", 0x806e3d04U, 0, false, false,
    5657        "test.s:1:16: Error: Expected 1 scalar register\n" },
     58    /* SOP2 instructions */
     59    { "        s_mul_hi_u32    s21, s4, s61\n", 0x96153d04U, 0, false, true, "" },
     60    { "        s_mul_hi_i32    s21, s4, s61\n", 0x96953d04U, 0, false, true, "" },
     61    { "        s_lshl1_add_u32 s21, s4, s61\n", 0x97153d04U, 0, false, true, "" },
     62    { "        s_lshl2_add_u32 s21, s4, s61\n", 0x97953d04U, 0, false, true, "" },
     63    { "        s_lshl3_add_u32 s21, s4, s61\n", 0x98153d04U, 0, false, true, "" },
     64    { "        s_lshl4_add_u32 s21, s4, s61\n", 0x98953d04U, 0, false, true, "" },
     65    { "        s_pack_ll_b32_b16 s21, s4, s61\n", 0x99153d04U, 0, false, true, "" },
     66    { "        s_pack_lh_b32_b16 s21, s4, s61\n", 0x99953d04U, 0, false, true, "" },
     67    { "        s_pack_hh_b32_b16 s21, s4, s61\n", 0x9a153d04U, 0, false, true, "" },
     68    /* SOP1 instructions */
     69    { "s_andn1_saveexec_b64 s[86:87], s[20:21]\n", 0xbed63314U, 0, false, true, "" },
     70    { "s_orn1_saveexec_b64 s[86:87], s[20:21]\n", 0xbed63414U, 0, false, true, "" },
     71    { "s_andn1_wrexec_b64 s[86:87], s[20:21]\n", 0xbed63514U, 0, false, true, "" },
     72    { "s_andn2_wrexec_b64 s[86:87], s[20:21]\n", 0xbed63614U, 0, false, true, "" },
     73    { "s_bitreplicate_b64_b32 s[86:87], s20\n", 0xbed63714U, 0, false, true, "" },
     74    /* SOPK instructions */
     75    { "s_call_b64 s[44:45], xxxx+8\nxxxx:", 0xbaac0002U, 0, false, true, "" },
     76    /* SOPP instructions */
     77    { "        s_endpgm_ordered_ps_done\n", 0xbf9e0000U, 0, false, true, "" },
    5778    { nullptr, 0, 0, false, false, 0 }
    5879};
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