Changeset 3129 in CLRX


Ignore:
Timestamp:
Jun 4, 2017, 1:31:44 PM (2 years ago)
Author:
matszpk
Message:

CLRadeonExtender: CLRXDoc: Add info about GPR indexing. Add info about S_ENDPGM_SAVED

Location:
CLRadeonExtender/trunk/doc
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/doc/GcnInstrsSopc.md

    r1722 r3129  
    241241```
    242242
     243#### S_SET_GPR_IDX_ON
     244
     245Opcode: 17 (0x11) for GCN 1.2 
     246Syntax:S_SET_GPR_IDX_ON SSRC0(0), IMM8 
     247Description: Enable GPR indexing mode. Set mode and index for GPR indexing. The mode
     248and index for GPR indexing are in M0. Refer to GPR indexing mode in [GcnOperands] 
     249Operation: 
     250```
     251MODE.gpr_idx_en = 1
     252M0 = (M0 & 0xffff0f00) | ((IMM8 & 15)<<12) | (SSRC0 & 0xff)
     253```
     254
    243255#### S_SETVSKIP
    244256
  • CLRadeonExtender/trunk/doc/GcnInstrsSopp.md

    r2443 r3129  
    169169Description: End program.
    170170
     171#### S_ENDPGM_SAVED
     172
     173Opcode: 27 (0x1b) for GCN 1.2 
     174Syntax: S_ENDPGM_SAVED 
     175Description: End of program; signal that a wave has been saved by the context-switch trap handler, and
     176terminate wavefront. The hardware implicitly executes S_WAITCNT 0 before executing this
     177instruction. Use S_ENDPGM in all cases unless you are executing the context-switch save
     178handler. (from ISA manual)
     179
    171180#### S_ICACHE_INV
    172181
  • CLRadeonExtender/trunk/doc/GcnOperands.md

    r3098 r3129  
    173173The HW registers and send message parameters (message and GSOP) is parametrizable if
    174174they will be preceded by `@` (example: `hwreg(@5, 8, 16)`).
     175
     176### GPR indexing mode (GCN 1.2)
     177
     178The GCN 1.2 introduces the GPR indexing mode that facilitate usage of indexing in VGPR's.
     179The bit 27 in MODE register indicates whether this mode is enabled.
     180The M0 register holds index and mode of GPR indexing. If this mode will be enabled
     181then this index will be added to index of specified VGPR used in vector instruction.
     182The mode specifies to which operand of vector instruction GPR index will be added.
     183If sum of GPR index and VGPR register index beyond last available VGPR register or
     184this is not a VGPR register (SGPR or other), then operand register will be substituted by
     185V0 register.
     186
     187The lowest 8 bits of M0 register holds the GPR index. The 12-15 bits holds GPR indexing mode.
     188The GPR indexing mode bits table:
     189
     190Bit | Description
     191----|--------------------------------------
     192 0  | Apply GPR indexing to VSRC0 operand
     193 1  | Apply GPR indexing to VSRC1 operand
     194 2  | Apply GPR indexing to VSRC2 operand
     195 3  | Apply GPR indexing to VDST operand
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