Changeset 3132 in CLRX


Ignore:
Timestamp:
Jun 4, 2017, 3:42:06 PM (23 months ago)
Author:
matszpk
Message:

CLRadeonExtender: CLRXDocs: Move GPR indexing to GcnState chapter.

Location:
CLRadeonExtender/trunk/doc
Files:
2 edited

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Unmodified
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Removed
  • CLRadeonExtender/trunk/doc/GcnOperands.md

    r3129 r3132  
    173173The HW registers and send message parameters (message and GSOP) is parametrizable if
    174174they will be preceded by `@` (example: `hwreg(@5, 8, 16)`).
    175 
    176 ### GPR indexing mode (GCN 1.2)
    177 
    178 The GCN 1.2 introduces the GPR indexing mode that facilitate usage of indexing in VGPR's.
    179 The bit 27 in MODE register indicates whether this mode is enabled.
    180 The M0 register holds index and mode of GPR indexing. If this mode will be enabled
    181 then this index will be added to index of specified VGPR used in vector instruction.
    182 The mode specifies to which operand of vector instruction GPR index will be added.
    183 If sum of GPR index and VGPR register index beyond last available VGPR register or
    184 this is not a VGPR register (SGPR or other), then operand register will be substituted by
    185 V0 register.
    186 
    187 The lowest 8 bits of M0 register holds the GPR index. The 12-15 bits holds GPR indexing mode.
    188 The GPR indexing mode bits table:
    189 
    190 Bit | Description
    191 ----|--------------------------------------
    192  0  | Apply GPR indexing to VSRC0 operand
    193  1  | Apply GPR indexing to VSRC1 operand
    194  2  | Apply GPR indexing to VSRC2 operand
    195  3  | Apply GPR indexing to VDST operand
  • CLRadeonExtender/trunk/doc/GcnState.md

    r2384 r3132  
    129129The initial value of FP_ROUND and FP_DENORM fields (first 8 bits in MODE register)
    130130can be given by including .floatmode pseudo-operation.
     131
     132### GPR indexing mode (GCN 1.2)
     133
     134The GCN 1.2 introduces the GPR indexing mode that facilitate usage of indexing in VGPR's.
     135The bit 27 in MODE register indicates whether this mode is enabled.
     136The M0 register holds index and mode of GPR indexing. If this mode will be enabled
     137then this index will be added to index of specified VGPR used in vector instruction.
     138The mode specifies to which operand of vector instruction a GPR index will be added.
     139If sum of GPR index and VGPR register index beyond last available VGPR register or
     140this is not a VGPR register (SGPR or other), then operand register will be substituted by
     141V0 register.
     142
     143The lowest 8 bits of M0 register holds the GPR index. The 12-15 bits holds GPR indexing mode.
     144The GPR indexing mode bits table:
     145
     146Bit | Description
     147----|--------------------------------------
     148 0  | Apply GPR indexing to VSRC0 operand
     149 1  | Apply GPR indexing to VSRC1 operand
     150 2  | Apply GPR indexing to VSRC2 operand
     151 3  | Apply GPR indexing to VDST operand
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