Changeset 3148 in CLRX


Ignore:
Timestamp:
Jun 10, 2017, 9:53:44 AM (2 years ago)
Author:
matszpk
Message:

CLRadeonExtender: CLRXDocs: Describe some V_*_F16 (half precision) instructions (VOP2).

Location:
CLRadeonExtender/trunk/doc
Files:
2 edited

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  • CLRadeonExtender/trunk/doc/GcnInstrsVop2.md

    r2450 r3148  
    6161NOTE: OMOD and CLAMP modifier affects only for instruction that output is
    6262floating point value. 
    63 NOTE: ABS and negation is applied to source operand for any instruction.
     63NOTE: ABS and negation is applied to source operand for any instruction. 
     64OMOD: OMOD modifier doesn't work for half precision (FP16) instructions (except V_MAC_F16).
    6465
    6566Negation and absolute value can be combined: `-ABS(V0)`. Modifiers CLAMP and
     
    138139Alphabetically sorted instruction list:
    139140
     141#### V_ADD_F16
     142
     143Opcode VOP2: 31 (0x1f) for GCN 1.2 
     144Opcode VOP3A: 287 (0x11f) for GCN 1.2 
     145Syntax: V_ADD_F16 VDST, SRC0, SRC1 
     146Description: Add two FP16 values from SRC0 and SRC1 and store result to VDST. 
     147Operation: 
     148```
     149VDST = ASHALF(SRC0) + ASHALF(SRC1)
     150```
     151
    140152#### V_ADD_F32
    141153
     
    415427```
    416428
     429#### V_MAC_F16
     430
     431Opcode VOP2: 35 (0x23) for GCN 1.2 
     432Opcode VOP3A: 291 (0x123) for GCN 1.2 
     433Syntax: V_MAC_F16 VDST, SRC0, SRC1 
     434Description: Multiply FP16 value from SRC0 by FP16 value from SRC1 and add result to VDST. 
     435Operation: 
     436```
     437VDST = ASHALF(SRC0) * ASHALF(SRC1) + ASHALF(VDST)
     438```
     439
    417440#### V_MAC_F32
    418441
     
    437460if (ASFLOAT(SRC0)!=0.0 && ASFLOAT(SRC1)!=0.0)
    438461    VDST = ASFLOAT(SRC0) * ASFLOAT(SRC1) + ASFLOAT(VDST)
     462```
     463
     464#### V_MADMK_F16
     465
     466Opcode: 36 (0x24) for GCN 1.2 
     467Opcode: 292 (0x124) for GCN 1.2 
     468Syntax: V_MADMK_F16 VDST, SRC0, FLOAT16LIT, SRC1 
     469Description: Multiply FP16 value from SRC0 with the constant literal FLOAT16LIT and add
     470FP16 value from SRC1; and store result to VDST. Constant literal follows
     471after instruction word. Use nearest-even rouding. 
     472Operation:
     473```
     474VDST = ASHALF(SRC0) * ASHALF(FLOAT16LIT) + ASHALF(SRC1)
    439475```
    440476
     
    452488```
    453489
     490#### V_MADAK_F16
     491
     492Opcode: 37 (0x25) for GCN 1.2 
     493Opcode: 293 (0x125) for GCN 1.2 
     494Syntax: V_MADAK_F16 VDST, SRC0, SRC1, FLOAT16LIT 
     495Description: Multiply FP16 value from SRC0 with FP16 value from SRC1 and add
     496the constant literal FLOATLIT16; and store result to VDST. Constant literal follows
     497after instruction word. 
     498Operation:
     499```
     500VDST = ASHALF(SRC0) * ASHALF(SRC1) + ASHALF(FLOAT16LIT)
     501```
     502
    454503#### V_MADAK_F32
    455504
     
    608657```
    609658
     659#### V_MUL_F16
     660
     661Opcode VOP2: 34 (0x22) for GCN 1.2 
     662Opcode VOP3A: 290 (0x122) for GCN 1.2 
     663Syntax: V_MUL_F16 VDST, SRC0, SRC1 
     664Description: Multiply FP16 value from SRC0 by FP16 value from SRC1
     665and store result to VDST. 
     666Operation: 
     667```
     668VDST = ASHALF(SRC0) * ASHALF(SRC1)
     669```
     670
    610671#### V_MUL_F32
    611672
     
    695756```
    696757SDST = VSRC0[SSRC1 & 63]
     758```
     759
     760#### V_SUB_F16
     761
     762Opcode VOP2: 32 (0x20) for GCN 1.2 
     763Opcode VOP3A: 288 (0x120) for GCN 1.2 
     764Syntax: V_SUB_F16 VDST, SRC0, SRC1 
     765Description: Subtract FP16 value of SRC1 from FP16 value of SRC0 and store result to VDST. 
     766Operation: 
     767```
     768VDST = ASHALF(SRC0) - ASHALF(SRC1)
    697769```
    698770
     
    768840```
    769841
     842#### V_SUBREV_F16
     843
     844Opcode VOP2: 33 (0x21) for GCN 1.2 
     845Opcode VOP3A: 289 (0x121) for GCN 1.2 
     846Syntax: V_SUBREV_F16 VDST, SRC0, SRC1 
     847Description: Subtract FP16 value of SRC0 from FP16 value of SRC1 and store result to VDST. 
     848Operation: 
     849```
     850VDST = ASHALF(SRC1) - ASHALF(SRC0)
     851```
     852
    770853#### V_SUBREV_F32
    771854
  • CLRadeonExtender/trunk/doc/GcnIsa.md

    r3144 r3148  
    5353* ISNAN(v) - return true if value v is NAN value
    5454
     55Shortcuts:
     56
     57* FP - floating point (default single if not specified)
     58* FP16 - half floating point
     59* FP32 - single floating point
     60* FP64 - double floating point
     61
    5562By default, any register value is treated as unsigned integer.
    5663
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