Changeset 3149 in CLRX


Ignore:
Timestamp:
Jun 10, 2017, 11:02:05 AM (2 years ago)
Author:
matszpk
Message:

CLRadeonExtender: CLRXDocs: Describe all 16-bit VOP2 instructions.

File:
1 edited

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  • CLRadeonExtender/trunk/doc/GcnInstrsVop2.md

    r3148 r3149  
    181181```
    182182
     183#### V_ADD_U16
     184
     185Opcode VOP2: 38 (0x26) for GCN 1.2 
     186Opcode VOP3A: 294 (0x126) for GCN 1.2 
     187Syntax: V_ADD_U16 VDST, SRC0, SRC1 
     188Description: Add two 16-bit unsigned values from SRC0 and SRC1 and
     189store 16-bit unsigned result to VDST. 
     190Operation: 
     191```
     192VDST = (SRC0 + SRC1) & 0xffff
     193```
     194
    183195#### V_ADDC_U32
    184196
     
    223235```
    224236
     237#### V_ASHRREV_B16
     238
     239Opcode VOP2: 44 (0x2c) for GCN 1.2 
     240Opcode VOP3A: 300 (0x12c) for GCN 1.2 
     241Syntax: V_ASHRREV_B16 VDST, SRC0, SRC1 
     242Description: Shift right signed 16-bit value from SRC1 by (SRC0&15) bits and
     243store 16-bit signed result into VDST. 
     244Operation: 
     245```
     246VDST = ((INT16)SRC1 >> (SRC0&15)) & 0xffff
     247```
     248
    225249#### V_ASHRREV_I32
    226250
     
    371395```
    372396
     397#### V_LDEXP_F16
     398
     399Opcode VOP2: 51 (0x33) for GCN 1.2 
     400Opcode VOP3A: 307 (0x133) for GCN 1.2 
     401Syntax: V_LDEXP_F16 VDST, SRC0, SRC1 
     402Description: Do ldexp operation on SRC0 and SRC1 (multiply SRC0 by 2**(SRC1)).
     403SRC1 is signed integer, SRC0 is half floating point value. 
     404Operation: 
     405```
     406VDST = ASHALF(SRC0) * POW(2.0, (INT32)SRC1)
     407```
     408
    373409#### V_LDEXP_F32
    374410
     
    394430```
    395431
     432#### V_LSHLREV_B16
     433
     434Opcode VOP2: 42 (0x2a) for GCN 1.2 
     435Opcode VOP3A: 298 (0x12a) for GCN 1.2 
     436Syntax: V_LSHLREV_B16 VDST, SRC0, SRC1 
     437Description: Shift left unsigned 16-bit value from SRC1 by (SRC0&15) bits and
     438store 16-bit unsigned result into VDST. 
     439Operation: 
     440```
     441VDST = (SRC1 << (SRC0&15)) & 0xffff
     442```
     443
    396444#### V_LSHLREV_B32
    397445
     
    416464```
    417465
     466#### V_LSHRREV_B16
     467
     468Opcode VOP2: 43 (0x2b) for GCN 1.2 
     469Opcode VOP3A: 299 (0x12b) for GCN 1.2 
     470Syntax: V_LSHRREV_B16 VDST, SRC0, SRC1 
     471Description: Shift right unsigned 16-bit value from SRC1 by (SRC0&15) bits and
     472store 16-bit unsigned result into VDST. 
     473Operation: 
     474```
     475VDST = (SRC1 >> (SRC0&15)) & 0xffff
     476```
     477
    418478#### V_LSHRREV_B32
    419479
     
    432492Opcode VOP3A: 291 (0x123) for GCN 1.2 
    433493Syntax: V_MAC_F16 VDST, SRC0, SRC1 
    434 Description: Multiply FP16 value from SRC0 by FP16 value from SRC1 and add result to VDST. 
     494Description: Multiply FP16 value from SRC0 by FP16 value from SRC1 and
     495add result to VDST. It applies OMOD modifier to result. 
    435496Operation: 
    436497```
     
    514575```
    515576
     577#### V_MAX_F16
     578
     579Opcode VOP2: 45 (0x2d) for GCN 1.2 
     580Opcode VOP3A: 301 (0x12d) for GCN 1.2 
     581Syntax: V_MAX_F16 VDST, SRC0, SRC1 
     582Description: Choose largest half floating point value from SRC0 and SRC1,
     583and store result to VDST. 
     584Operation: 
     585```
     586VDST = MAX(ASFHALF(SRC0), ASFHALF(SRC1))
     587```
     588
    516589#### V_MAX_F32
    517590
     
    592665```
    593666
     667#### V_MIN_F16
     668
     669Opcode VOP2: 46 (0x2e) for GCN 1.2 
     670Opcode VOP3A: 302 (0x12e) for GCN 1.2 
     671Syntax: V_MIN_F16 VDST, SRC0, SRC1 
     672Description: Choose smallest half floating point value from SRC0 and SRC1,
     673and store result to VDST. 
     674Operation: 
     675```
     676VDST = MIN(ASFHALF(SRC0), ASFHALF(SRC1))
     677```
     678
    594679#### V_MIN_F32
    595680
     
    602687```
    603688VDST = MIN(ASFLOAT(SRC0), ASFLOAT(SRC1))
     689```
     690
     691#### V_MIN_i16
     692
     693Opcode VOP2: 50 (0x32) for GCN 1.2 
     694Opcode VOP3A: 306 (0x132) for GCN 1.2 
     695Syntax: V_MIN_i16 VDST, SRC0, SRC1 
     696Description: Choose smallest signed 16-bit value from SRC0 and SRC1,
     697and store result to VDST. 
     698Operation: 
     699```
     700VDST = MIN((INT16)SRC0, (INT16)SRC1)
    604701```
    605702
     
    631728```
    632729
     730#### V_MIN_U16
     731
     732Opcode VOP2: 49 (0x31) for GCN 1.2 
     733Opcode VOP3A: 305 (0x131) for GCN 1.2 
     734Syntax: V_MIN_U16 VDST, SRC0, SRC1 
     735Description: Choose smallest unsigned 16-bit value from SRC0 and SRC1,
     736and store result to VDST. 
     737Operation: 
     738```
     739VDST = MIN(SRC0&0xffff, SRC1&0xffff)
     740```
     741
    633742#### V_MIN_U32
    634743
     
    722831```
    723832
     833#### V_MUL_LO_U16
     834
     835Opcode VOP2: 41 (0x29) for GCN 1.2 
     836Opcode VOP3A: 297 (0x129) for GCN 1.2 
     837Syntax: V_MUL_LO_U16 VDST, SRC0, SRC1 
     838Description: Multiply 16-bit unsigned value from SRC0 by 16-bit unsigned value from SRC1
     839and store 16-bit result to VDST. 
     840Operation: 
     841```
     842VDST = ((SRC0&0Xffff) * (SRC1&0xffff)) & 0xffff
     843```
     844
    724845#### V_MUL_U32_U24
    725846
     
    778899```
    779900VDST = ASFLOAT(SRC0) - ASFLOAT(SRC1)
     901```
     902
     903#### V_SUB_U16
     904
     905Opcode VOP2: 39 (0x27) for GCN 1.2 
     906Opcode VOP3A: 295 (0x127) for GCN 1.2 
     907Syntax: V_SUB_U16 VDST, SRC0, SRC1 
     908Description: Subtract unsigned 16-bit value of SRC1 from SRC0 and store
     90916-bit unsigned result to VDST. 
     910Operation: 
     911```
     912VDST = (SRC0 - SRC1) & 0xffff
    780913```
    781914
     
    8821015```
    8831016
     1017#### V_SUBREV_U16
     1018
     1019Opcode VOP2: 40 (0x28) for GCN 1.2 
     1020Opcode VOP3A: 296 (0x128) for GCN 1.2 
     1021Syntax: V_SUBREV_U16 VDST, SRC0, SRC1 
     1022Description: Subtract unsigned 16-bit value of SRC0 from SRC1 and store
     102316-bit unsigned result to VDST. 
     1024Operation: 
     1025```
     1026VDST = (SRC1 - SRC0) & 0xffff
     1027```
     1028
    8841029#### V_XOR_B32
    8851030
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