Ignore:
Timestamp:
Jun 16, 2017, 6:41:29 PM (3 years ago)
Author:
matszpk
Message:

CLRadeonExtender: CLRXDocs: Add info about applying MODE to half precision operations.
Update info denormals flushing to V_MAD*/V_MAC* instructions.

File:
1 edited

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  • CLRadeonExtender/trunk/doc/GcnInstrsVop1.md

    r3150 r3165  
    6161floating point value. 
    6262NOTE: ABS and negation is applied to source operand for any instruction. 
    63 NOTE: OMOD modifier doesn't work for half precision (FP16) instructions.
    6463
    6564Negation and absolute value can be combined: `-ABS(V0)`. Modifiers CLAMP and
     
    313312Description: Convert single FP value to half floating point value with rounding from
    314313MODE register (single FP rounding mode), and store result to VDST.
    315 If absolute value is too high, then store -/+infinity to VDST. 
     314If absolute value is too high, then store -/+infinity to VDST.
     315In GCN 1.2 flushing denormals controlled by MODE. In GCN 1.0/1.1, denormals are enabled. 
    316316Operation: 
    317317```
    318318VDST = CVTHALF(ASFLOAT(SRC0))
     319```
     320
     321#### V_CVT_F16_U16
     322
     323Opcode: VOP1: 57 (0x39) for GCN 1.2 
     324Opcode VOP3A: 377 (0x179) for GCN 1.2 
     325Syntax: V_CVT_F16_U16 VDST, SRC0 
     326Description: Convert 16-bit unsigned valut to half floating point value. 
     327Operation: 
     328```
     329VDST = (HALF)SRC0
    319330```
    320331
     
    325336Syntax: V_CVT_F32_F16 VDST, SRC0 
    326337Description: Convert half FP value to single FP value, and store result to VDST.
    327 **By default, immediate is in FP32 format!**. 
     338**By default, immediate is in FP32 format!**.
     339In GCN 1.2 flushing denormals controlled by MODE. In GCN 1.0/1.1, denormals are enabled. 
    328340Operation: 
    329341```
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