Changeset 3169 in CLRX
 Timestamp:
 Jun 17, 2017, 9:12:03 AM (2 years ago)
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CLRadeonExtender/trunk/doc/GcnInstrsVop1.md
r3167 r3169 488 488 ``` 489 489 490 #### V_CVT_I16_F16 491 492 Opcode VOP1: 60 (0x3c) 493 Opcode VOP3A: 380 (0x17c) for GCN 1.2 494 Syntax: V_CVT_I16_F16 VDST, SRC0 495 Description: Convert 16bit floating point value from SRC0 to signed 16bit integer, and 496 store result to VDST. Conversion uses rounding to zero. If value is higher/lower than 497 maximal/minimal integer then store MAX_INT16/MIN_INT16 to VDST. 498 If input value is NaN then store 0 to VDST. 499 Operation: 500 ``` 501 VDST = 0 502 if (!ISNAN(ASHALF(SRC0))) 503 VDST = (INT16)MAX(MIN(RNDTZINT(ASHALF(SRC0)), 32767.0), 32768.0) 504 ``` 505 490 506 #### V_CVT_I32_F32 491 507 … … 550 566 ``` 551 567 568 #### V_CVT_U16_F16 569 570 Opcode VOP1: 59 (0x3b) for GCN 1.2 571 Opcode VOP3A: 379 (0x17b) for GCN 1.2 572 Syntax: V_CVT_U16_F16 VDST, SRC0 573 Description: Convert 32bit half floating point value from SRC0 to unsigned 16bit integer, 574 and store result to VDST. Conversion uses rounding to zero. If value is higher than 575 maximal integer then store MAX_UINT16 to VDST. If input value is NaN then store 0 to VDST. 576 Operation: 577 ``` 578 VDST = 0 579 if (!ISNAN(ASHALF(SRC0))) 580 VDST = (UINT16)MIN(RNDTZINT(ASHALF(SRC0)), 65535.0) 581 ``` 582 583 552 584 #### V_CVT_U32_F32 553 585 … … 582 614 ``` 583 615 616 #### V_EXP_F16 617 618 Opcode VOP1: 65 (0x41) for GCN 1.2 619 Opcode VOP3A: 385 (0x181) for GCN 1.2 620 Syntax: V_EXP_F16 VDST, SRC0 621 Description: Approximate power of two from half FP value SRC0 and store it to VDST. 622 Instruction always handles dernomals in output regardless floatmode in MODE register. 623 Operation: 624 ``` 625 VDST = APPROX_POW2(ASHALF(SRC0)) 626 ``` 627 584 628 #### V_EXP_F32 585 629 … … 811 855 ``` 812 856 857 #### V_LOG_F16 858 859 Opcode VOP1: 64 (0x40) for GCN 1.2 860 Opcode VOP3A: 384 (0x180) for GCN 1.2 861 Syntax: V_LOG_F16 VDST, SRC0 862 Description: Approximate logarithm of base 2 from half floating point value SRC0, and store 863 result to VDST. If SRC0 is negative then store NaN to VDST. 864 This instruction handle denormalized values regardless FLOAT MODE register setup. 865 Operation: 866 ``` 867 HALF F = ASHALF(SRC0) 868 if (F==1.0) 869 VDST = 0.0h 870 if (F<0.0) 871 VDST = NaN_F 872 else 873 VDST = APPROX_LOG2(F) 874 ``` 875 813 876 #### V_LOG_F32 814 877 … … 949 1012 ``` 950 1013 1014 #### V_RCP_F16 1015 1016 Opcode VOP1: 61 (0x3d) for GCN 1.2 1017 Opcode VOP3A: 381 (0x17d) for GCN 1.2 1018 Syntax: V_RCP_F16 VDST, SRC0 1019 Description: Approximate reciprocal from half floating point value SRC0 and 1020 store it to VDST. Guaranted error below 1ulp. 1021 Operation: 1022 ``` 1023 VDST = APPROX_RCP(ASHALF(SRC0)) 1024 ``` 1025 951 1026 #### V_RCP_F32 952 1027 … … 1076 1151 if (ASDOUBLE(VDST)==INF) 1077 1152 VDST = MAX_DOUBLE 1153 ``` 1154 1155 #### V_RSQ_F16 1156 1157 Opcode VOP1: 63 (0x3f) for GCN 1.2 1158 Opcode VOP3A: 383 (0x17f) for GCN 1.2 1159 Syntax: V_RSQ_F16 VDST, SRC0 1160 Description: Approximate reciprocal square root from half floating point value SRC0 and 1161 store it to VDST. If SRC0 is negative value, store NAN to VDST. 1162 This instruction doesn't handle denormalized values regardless FLOAT MODE register setup. 1163 Operation: 1164 ``` 1165 VDST = APPROX_RSQRT(ASHALF(SRC0)) 1078 1166 ``` 1079 1167 … … 1139 1227 ``` 1140 1228 1229 #### V_SQRT_F16 1230 1231 Opcode VOP1: 62 (0x3e) for GCN 1.2 1232 Opcode VOP3A: 382 (0x17e) for GCN 1.2 1233 Syntax: V_SQRT_F16 VDST, SRC0 1234 Description: Compute square root of half floating point value SRC0, and 1235 store result to VDST. If SRC0 is negative value then store NaN to VDST. 1236 Operation: 1237 ``` 1238 if (ASHALF(SRC0)>=0.0) 1239 VDST = APPROX_SQRT(ASHALF(SRC0)) 1240 else 1241 VDST = NAN_H 1242 ``` 1243 1141 1244 #### V_SQRT_F32 1142 1245
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