Changeset 3169 in CLRX


Ignore:
Timestamp:
Jun 17, 2017, 9:12:03 AM (20 months ago)
Author:
matszpk
Message:

CLRadeonExtender: CLRXDocs: Add descriptions of new GCN1.2 VOP1 instructions.

File:
1 edited

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  • CLRadeonExtender/trunk/doc/GcnInstrsVop1.md

    r3167 r3169  
    488488```
    489489
     490#### V_CVT_I16_F16
     491
     492Opcode VOP1: 60 (0x3c) 
     493Opcode VOP3A: 380 (0x17c) for GCN 1.2 
     494Syntax: V_CVT_I16_F16 VDST, SRC0 
     495Description: Convert 16-bit floating point value from SRC0 to signed 16-bit integer, and
     496store result to VDST. Conversion uses rounding to zero. If value is higher/lower than
     497maximal/minimal integer then store MAX_INT16/MIN_INT16 to VDST.
     498If input value is NaN then store 0 to VDST. 
     499Operation: 
     500```
     501VDST = 0
     502if (!ISNAN(ASHALF(SRC0)))
     503    VDST = (INT16)MAX(MIN(RNDTZINT(ASHALF(SRC0)), 32767.0), -32768.0)
     504```
     505
    490506#### V_CVT_I32_F32
    491507
     
    550566```
    551567
     568#### V_CVT_U16_F16
     569
     570Opcode VOP1: 59 (0x3b) for GCN 1.2 
     571Opcode VOP3A: 379 (0x17b) for GCN 1.2 
     572Syntax: V_CVT_U16_F16 VDST, SRC0 
     573Description: Convert 32-bit half floating point value from SRC0 to unsigned 16-bit integer,
     574and store result to VDST. Conversion uses rounding to zero. If value is higher than
     575maximal integer then store MAX_UINT16 to VDST. If input value is NaN then store 0 to VDST. 
     576Operation: 
     577```
     578VDST = 0
     579if (!ISNAN(ASHALF(SRC0)))
     580    VDST = (UINT16)MIN(RNDTZINT(ASHALF(SRC0)), 65535.0)
     581```
     582
     583
    552584#### V_CVT_U32_F32
    553585
     
    582614```
    583615
     616#### V_EXP_F16
     617
     618Opcode VOP1: 65 (0x41) for GCN 1.2 
     619Opcode VOP3A: 385 (0x181) for GCN 1.2 
     620Syntax: V_EXP_F16 VDST, SRC0 
     621Description: Approximate power of two from half FP value SRC0 and store it to VDST.
     622Instruction always handles dernomals in output regardless floatmode in MODE register. 
     623Operation: 
     624```
     625VDST = APPROX_POW2(ASHALF(SRC0))
     626```
     627
    584628#### V_EXP_F32
    585629
     
    811855```
    812856
     857#### V_LOG_F16
     858
     859Opcode VOP1: 64 (0x40) for GCN 1.2 
     860Opcode VOP3A: 384 (0x180) for GCN 1.2 
     861Syntax: V_LOG_F16 VDST, SRC0 
     862Description: Approximate logarithm of base 2 from half floating point value SRC0, and store
     863result to VDST. If SRC0 is negative then store -NaN to VDST.
     864This instruction handle denormalized values regardless FLOAT MODE register setup. 
     865Operation: 
     866```
     867HALF F = ASHALF(SRC0)
     868if (F==1.0)
     869    VDST = 0.0h
     870if (F<0.0)
     871    VDST = -NaN_F
     872else
     873    VDST = APPROX_LOG2(F)
     874```
     875
    813876#### V_LOG_F32
    814877
     
    9491012```
    9501013
     1014#### V_RCP_F16
     1015
     1016Opcode VOP1: 61 (0x3d) for GCN 1.2 
     1017Opcode VOP3A: 381 (0x17d) for GCN 1.2 
     1018Syntax: V_RCP_F16 VDST, SRC0 
     1019Description: Approximate reciprocal from half floating point value SRC0 and
     1020store it to VDST. Guaranted error below 1ulp. 
     1021Operation: 
     1022```
     1023VDST = APPROX_RCP(ASHALF(SRC0))
     1024```
     1025
    9511026#### V_RCP_F32
    9521027
     
    10761151if (ASDOUBLE(VDST)==INF)
    10771152    VDST = MAX_DOUBLE
     1153```
     1154
     1155#### V_RSQ_F16
     1156
     1157Opcode VOP1: 63 (0x3f) for GCN 1.2 
     1158Opcode VOP3A: 383 (0x17f) for GCN 1.2 
     1159Syntax: V_RSQ_F16 VDST, SRC0 
     1160Description: Approximate reciprocal square root from half floating point value SRC0 and
     1161store it to VDST. If SRC0 is negative value, store -NAN to VDST.
     1162This instruction doesn't handle denormalized values regardless FLOAT MODE register setup. 
     1163Operation: 
     1164```
     1165VDST = APPROX_RSQRT(ASHALF(SRC0))
    10781166```
    10791167
     
    11391227```
    11401228
     1229#### V_SQRT_F16
     1230
     1231Opcode VOP1: 62 (0x3e) for GCN 1.2 
     1232Opcode VOP3A: 382 (0x17e) for GCN 1.2 
     1233Syntax: V_SQRT_F16 VDST, SRC0 
     1234Description: Compute square root of half floating point value SRC0, and
     1235store result to VDST. If SRC0 is negative value then store -NaN to VDST. 
     1236Operation: 
     1237```
     1238if (ASHALF(SRC0)>=0.0)
     1239    VDST = APPROX_SQRT(ASHALF(SRC0))
     1240else
     1241    VDST = -NAN_H
     1242```
     1243
    11411244#### V_SQRT_F32
    11421245
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