Changeset 3194 in CLRX


Ignore:
Timestamp:
Jun 27, 2017, 12:22:09 PM (3 years ago)
Author:
matszpk
Message:

CLRadeonExtender: CLRXDocs: Typos (Spgrs -> Sgprs). Add some Doxygen documentation.

Location:
CLRadeonExtender/trunk
Files:
9 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/CLRX/amdasm/AsmFormats.h

    r2999 r3194  
    202202    void writeBinary(std::ostream& os) const;
    203203    void writeBinary(Array<cxbyte>& array) const;
    204     const cxuint* getCurrentKernels(cxuint& kernelsNum) const;
    205204};
    206205
     
    420419};
    421420
     421/// ROCm kernel configuration
    422422struct AsmROCmKernelConfig: ROCmKernelConfig
    423423{
  • CLRadeonExtender/trunk/CLRX/amdbin/Commons.h

    r3156 r3194  
    4040
    4141enum {
    42     AMDHSAFLAG_USE_PRIVATE_SEGMENT_BUFFER = 1,
     42    AMDHSAFLAG_USE_PRIVATE_SEGMENT_BUFFER = 1,  ///<
    4343    AMDHSAFLAG_USE_DISPATCH_PTR = 2,
    4444    AMDHSAFLAG_USE_QUEUE_PTR = 4,
     
    6060};
    6161
    62 
     62/// AMD HSA kernel configuration structure
    6363struct AmdHsaKernelConfig
    6464{
    65     uint32_t amdCodeVersionMajor;
    66     uint32_t amdCodeVersionMinor;
    67     uint16_t amdMachineKind;
    68     uint16_t amdMachineMajor;
    69     uint16_t amdMachineMinor;
    70     uint16_t amdMachineStepping;
    71     uint64_t kernelCodeEntryOffset;
    72     uint64_t kernelCodePrefetchOffset;
     65    uint32_t amdCodeVersionMajor;   ///< AMD code version major number
     66    uint32_t amdCodeVersionMinor;   ///< AMD code version minor number
     67    uint16_t amdMachineKind;    ///< architecture kind
     68    uint16_t amdMachineMajor;   ///< arch major number
     69    uint16_t amdMachineMinor;   ///< arch minor number
     70    uint16_t amdMachineStepping;    ///< arch stepping number
     71    uint64_t kernelCodeEntryOffset;     ///< kernel relative to this config to kernel code
     72    uint64_t kernelCodePrefetchOffset;  ///< kernel code prefetch offset
    7373    uint64_t kernelCodePrefetchSize;
    7474    uint64_t maxScrachBackingMemorySize;
    75     uint32_t computePgmRsrc1;
    76     uint32_t computePgmRsrc2;
    77     uint16_t enableSpgrRegisterFlags;
    78     uint16_t enableFeatureFlags;
     75    uint32_t computePgmRsrc1;   ///< PGMRSRC1 register value
     76    uint32_t computePgmRsrc2;   ///< PGMRSRC2 register value
     77    uint16_t enableSgprRegisterFlags;   ///< bitfield of sg
     78    uint16_t enableFeatureFlags;    ///< bitfield of feature flags
    7979    uint32_t workitemPrivateSegmentSize;
    8080    uint32_t workgroupGroupSegmentSize;
  • CLRadeonExtender/trunk/CLRX/amdbin/ElfBinaries.h

    r2682 r3194  
    383383    { return reinterpret_cast<typename Types::Nhdr*>(noteTable); }
    384384   
     385    /// get size of notes in bytes
    385386    typename Types::Size getNotesSize() const
    386387    { return noteTableSize; }
     
    682683};
    683684
     685/// ELF note structure
    684686struct ElfNote
    685687{
    686     const char* name;
    687     size_t descSize;
    688     const cxbyte* desc;
    689     uint32_t type;
     688    const char* name;   ///< note name
     689    size_t descSize;    ///< description size
     690    const cxbyte* desc; ///< description
     691    uint32_t type;      ///< type
    690692};
    691693
  • CLRadeonExtender/trunk/CLRX/amdbin/ROCmBinaries.h

    r3156 r3194  
    4444enum : Flags {
    4545    ROCMBIN_CREATE_REGIONMAP = 0x10,    ///< create region map
    46    
    4746    ROCMBIN_CREATE_ALL = ELF_CREATE_ALL | 0xfff0 ///< all ROCm binaries flags
    4847};
     
    6261    size_t size;    ///< data size
    6362    size_t offset;     ///< data
    64     ROCmRegionType type;
     63    ROCmRegionType type; ///< type
    6564};
    6665
     
    7271{
    7372public:
     73    /// region map type
    7474    typedef Array<std::pair<CString, size_t> > RegionMap;
    7575private:
     
    8080    cxbyte* code;
    8181public:
     82    /// constructor
    8283    ROCmBinary(size_t binaryCodeSize, cxbyte* binaryCode,
    8384            Flags creationFlags = ROCMBIN_CREATE_ALL);
     85    /// default destructor
    8486    ~ROCmBinary() = default;
    8587   
     
    159161};
    160162
     163/// ROCm binary input structure
    161164struct ROCmInput
    162165{
     
    172175    std::vector<BinSymbol> extraSymbols;    ///< extra symbols
    173176   
     177    /// add empty kernel with default values
    174178    void addEmptyKernel(const char* kernelName);
    175179};
    176180
     181/// ROCm binary generator
    177182class ROCmBinGenerator: public NonCopyableAndNonMovable
    178183{
     
    185190             Array<cxbyte>* aPtr) const;
    186191public:
     192    /// constructor
    187193    ROCmBinGenerator();
    188194    /// constructor with ROCm input
    189195    ROCmBinGenerator(const ROCmInput* rocmInput);
    190196   
     197    /// constructor
     198    /**
     199     * \param deviceType device type
     200     * \param archMinor architecture minor number
     201     * \param archStepping architecture stepping number
     202     * \param codeSize size of code
     203     * \param code code pointer
     204     * \param symbols symbols (kernels, datas,...)
     205     */
    191206    ROCmBinGenerator(GPUDeviceType deviceType, uint32_t archMinor, uint32_t archStepping,
    192207            size_t codeSize, const cxbyte* code,
    193208            const std::vector<ROCmSymbolInput>& symbols);
     209    /// constructor
    194210    ROCmBinGenerator(GPUDeviceType deviceType, uint32_t archMinor, uint32_t archStepping,
    195211            size_t codeSize, const cxbyte* code,
    196212            std::vector<ROCmSymbolInput>&& symbols);
     213    /// destructor
    197214    ~ROCmBinGenerator();
    198215   
  • CLRadeonExtender/trunk/amdasm/AsmGalliumFormat.cpp

    r3164 r3194  
    13811381            SULEV(outConfig.computePgmRsrc1, pgmRSRC1);
    13821382            SULEV(outConfig.computePgmRsrc2, pgmRSRC2);
    1383             SULEV(outConfig.enableSpgrRegisterFlags,
     1383            SULEV(outConfig.enableSgprRegisterFlags,
    13841384                    uint16_t(AMDHSAFLAG_USE_PRIVATE_SEGMENT_BUFFER|
    13851385                        AMDHSAFLAG_USE_DISPATCH_PTR|AMDHSAFLAG_USE_KERNARG_SEGMENT_PTR));
  • CLRadeonExtender/trunk/amdasm/AsmROCmFormat.cpp

    r3026 r3194  
    296296        ::memset(config->controlDirective, 0, 128);
    297297        config->computePgmRsrc1 = config->computePgmRsrc2 = 0;
    298         config->enableSpgrRegisterFlags = 0;
     298        config->enableSgprRegisterFlags = 0;
    299299        config->enableFeatureFlags = 0;
    300300        config->reserved1[0] = config->reserved1[1] = config->reserved1[2] = 0;
     
    710710            break;
    711711        case ROCMCVAL_USE_PRIVATE_SEGMENT_BUFFER:
    712             config.enableSpgrRegisterFlags |= ROCMFLAG_USE_PRIVATE_SEGMENT_BUFFER;
     712            config.enableSgprRegisterFlags |= ROCMFLAG_USE_PRIVATE_SEGMENT_BUFFER;
    713713            break;
    714714        case ROCMCVAL_USE_DISPATCH_PTR:
    715             config.enableSpgrRegisterFlags |= ROCMFLAG_USE_DISPATCH_PTR;
     715            config.enableSgprRegisterFlags |= ROCMFLAG_USE_DISPATCH_PTR;
    716716            break;
    717717        case ROCMCVAL_USE_QUEUE_PTR:
    718             config.enableSpgrRegisterFlags |= ROCMFLAG_USE_QUEUE_PTR;
     718            config.enableSgprRegisterFlags |= ROCMFLAG_USE_QUEUE_PTR;
    719719            break;
    720720        case ROCMCVAL_USE_KERNARG_SEGMENT_PTR:
    721             config.enableSpgrRegisterFlags |= ROCMFLAG_USE_KERNARG_SEGMENT_PTR;
     721            config.enableSgprRegisterFlags |= ROCMFLAG_USE_KERNARG_SEGMENT_PTR;
    722722            break;
    723723        case ROCMCVAL_USE_DISPATCH_ID:
    724             config.enableSpgrRegisterFlags |= ROCMFLAG_USE_DISPATCH_ID;
     724            config.enableSgprRegisterFlags |= ROCMFLAG_USE_DISPATCH_ID;
    725725            break;
    726726        case ROCMCVAL_USE_FLAT_SCRATCH_INIT:
    727             config.enableSpgrRegisterFlags |= ROCMFLAG_USE_FLAT_SCRATCH_INIT;
     727            config.enableSgprRegisterFlags |= ROCMFLAG_USE_FLAT_SCRATCH_INIT;
    728728            break;
    729729        case ROCMCVAL_USE_PRIVATE_SEGMENT_SIZE:
    730             config.enableSpgrRegisterFlags |= ROCMFLAG_USE_PRIVATE_SEGMENT_SIZE;
     730            config.enableSgprRegisterFlags |= ROCMFLAG_USE_PRIVATE_SEGMENT_SIZE;
    731731            break;
    732732        case ROCMCVAL_USE_ORDERED_APPEND_GDS:
     
    941941    handler.kernelStates[asmr.currentKernel]->initializeKernelConfig();
    942942    uint16_t& flags = handler.kernelStates[asmr.currentKernel]->config->
    943                 enableSpgrRegisterFlags;
     943                enableSgprRegisterFlags;
    944944    flags = (flags & ~(7<<ROCMFLAG_USE_GRID_WORKGROUP_COUNT_BIT)) |
    945945            (dimMask<<ROCMFLAG_USE_GRID_WORKGROUP_COUNT_BIT);
     
    14871487        if (config.userDataNum == BINGEN8_DEFAULT)
    14881488        {   // calcuate userSGPRs
    1489             const uint16_t sgprFlags = config.enableSpgrRegisterFlags;
     1489            const uint16_t sgprFlags = config.enableSgprRegisterFlags;
    14901490            userSGPRsNum =
    14911491                ((sgprFlags&ROCMFLAG_USE_PRIVATE_SEGMENT_BUFFER)!=0 ? 4 : 0) +
     
    15291529            cxuint flags = kernelStates[i]->allocRegFlags |
    15301530                // flat_scratch_init
    1531                 ((config.enableSpgrRegisterFlags&ROCMFLAG_USE_FLAT_SCRATCH_INIT)!=0?
     1531                ((config.enableSgprRegisterFlags&ROCMFLAG_USE_FLAT_SCRATCH_INIT)!=0?
    15321532                            GCN_FLAT : 0) |
    15331533                // enable_xnack
     
    15881588        SLEV(config.computePgmRsrc1, config.computePgmRsrc1);
    15891589        SLEV(config.computePgmRsrc2, config.computePgmRsrc2);
    1590         SLEV(config.enableSpgrRegisterFlags, config.enableSpgrRegisterFlags);
     1590        SLEV(config.enableSgprRegisterFlags, config.enableSgprRegisterFlags);
    15911591        SLEV(config.enableFeatureFlags, config.enableFeatureFlags);
    15921592        SLEV(config.workitemPrivateSegmentSize, config.workitemPrivateSegmentSize);
  • CLRadeonExtender/trunk/amdasm/DisasmROCm.cpp

    r2710 r3194  
    7474    uint32_t computePgmRsrc1 = ULEV(config.computePgmRsrc1);
    7575    uint32_t computePgmRsrc2 = ULEV(config.computePgmRsrc2);
    76     uint16_t enableSpgrRegisterFlags = ULEV(config.enableSpgrRegisterFlags);
     76    uint16_t enableSgprRegisterFlags = ULEV(config.enableSgprRegisterFlags);
    7777    uint16_t enableFeatureFlags = ULEV(config.enableFeatureFlags);
    7878    uint32_t workitemPrivateSegmentSize = ULEV(config.workitemPrivateSegmentSize);
     
    181181    }
    182182   
    183     const uint16_t sgprFlags = enableSpgrRegisterFlags;
     183    const uint16_t sgprFlags = enableSgprRegisterFlags;
    184184    if ((sgprFlags&ROCMFLAG_USE_PRIVATE_SEGMENT_BUFFER) != 0)
    185185        output.write("        .use_private_segment_buffer\n", 36);
  • CLRadeonExtender/trunk/tests/amdasm/AsmROCmFormat.cpp

    r2682 r3194  
    8484            "      computePgmRsrc1=0x" << std::hex << ULEV(config.computePgmRsrc1) << "\n"
    8585            "      computePgmRsrc2=0x" << ULEV(config.computePgmRsrc2) << "\n"
    86             "      enableSpgrRegisterFlags=0x" <<
    87                 ULEV(config.enableSpgrRegisterFlags) << "\n"
     86            "      enableSgprRegisterFlags=0x" <<
     87                ULEV(config.enableSgprRegisterFlags) << "\n"
    8888            "      enableFeatureFlags=0x" <<
    8989                ULEV(config.enableFeatureFlags) << std::dec << "\n"
     
    219219      computePgmRsrc1=0x3c0000
    220220      computePgmRsrc2=0xa008081
    221       enableSpgrRegisterFlags=0x0
     221      enableSgprRegisterFlags=0x0
    222222      enableFeatureFlags=0x6
    223223      workitemPrivateSegmentSize=111
     
    255255      computePgmRsrc1=0xc0000
    256256      computePgmRsrc2=0x84
    257       enableSpgrRegisterFlags=0x8
     257      enableSgprRegisterFlags=0x8
    258258      enableFeatureFlags=0x0
    259259      workitemPrivateSegmentSize=0
     
    371371      computePgmRsrc1=0xa00c3ab4
    372372      computePgmRsrc2=0x3ed09291
    373       enableSpgrRegisterFlags=0x2a1
     373      enableSgprRegisterFlags=0x2a1
    374374      enableFeatureFlags=0x6c
    375375      workitemPrivateSegmentSize=33
  • CLRadeonExtender/trunk/utils/GPUId.cpp

    r3056 r3194  
    193193    if (regType == REGTYPE_VGPR)
    194194        return 256; // VGPRS
    195     cxuint maxSpgrs = (architecture==GPUArchitecture::GCN1_2) ? 102 : 104;
     195    cxuint maxSgprs = (architecture==GPUArchitecture::GCN1_2) ? 102 : 104;
    196196    if ((flags & REGCOUNT_NO_FLAT)!=0 && (architecture>GPUArchitecture::GCN1_0))
    197         maxSpgrs -= (architecture==GPUArchitecture::GCN1_2) ? 6 : 4;
     197        maxSgprs -= (architecture==GPUArchitecture::GCN1_2) ? 6 : 4;
    198198    else if ((flags & REGCOUNT_NO_XNACK)!=0 && (architecture>GPUArchitecture::GCN1_1))
    199         maxSpgrs -= 4;
     199        maxSgprs -= 4;
    200200    else if ((flags & REGCOUNT_NO_VCC)!=0)
    201         maxSpgrs -= 2;
    202     return maxSpgrs;
     201        maxSgprs -= 2;
     202    return maxSgprs;
    203203}
    204204
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