Changeset 4649 in CLRX


Ignore:
Timestamp:
Sep 20, 2018, 12:30:40 PM (5 weeks ago)
Author:
matszpk
Message:

CLRadeonExtender: Update change log.

File:
1 edited

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  • CLRadeonExtender/trunk/ChangeLog

    r3831 r4649  
    11
    22Change Log
     3
     4CLRadeonExtender 0.1.8:
     5
     6* add chapter about binary formats to CLRX documentation
     7* add some informations about compilation under FreeBSD
     8* add '.nosectdiffs' to disable new section difference behaviour if new ROCm format choosen
     9* small optimization in the AsmScope destructor.
     10* add extra info about setting up number of the SGPRs register in documentation
     11* fixed OpenCL detection for AMDGPU-PRO
     12* add '.enum' pseudo-op to simplify defining enumerations
     13* add CLRX_VERSION_NUMBER and CLRX_POLICY_UNIFIED_SGPR_COUNT
     14* add policy to unify SGPR counting for all binary formats (by default disabled)
     15* in documentation fix some some mistakes about building
     16* add preliminary support for CPU architectures (untested): SPARC, IA64 and MIPS
     17* add new '.dims' syntax for distinguish vector group ids and scalar local ids
     18* improve CLZ32/64 for MSVC
     19* introduce CTZ32/64
     20* while disassemblying determine minimal AMD driver version for GPU device type
     21  (better code detection while disassemblying)
     22* fixed some types in documentation
     23* update list of GPU devices in documentation
     24* fix stupid and old bug in ImageMix sample
     25* change a GPU device name for VEGA11 to GFX902
     26* fixed segfault when attempt to disassemble old Gallium binaries using new Gallium binary format
     27* sort the kernels by an offset order by disassemblying
     28* better input data checking while disassemblying code
     29* add HSALayout mode for AMDCL2 format (similar code layout like in ROCm and Gallium formats)
     30* introduce kernel code parts ('.kcode' and '.kcodeend') to AMDCL2
     31* check sanity of use LDS in AMD VEGA architecture (can be used only in SCRATCH and GLOBAL)
     32* in source code add new types: GPUArchMask, AsmKernelId and AsmSectionId type.
     33* allow constant literals in sym regranges
     34* fixed symreg ranges checking
     35* fixed handling some the symbol names similar to some register names (like exec_masc)
     36* add new GPU devices to list (gfx904, gfx905, gfx906 and gfx907)
     37* add AMD VEGA 20 instruction set
     38* add much stuff to handle register allocation (still it doesn't work and it wasnot finished)
     39* add a DTree structure to save memory in storing register allocation structures
     40* fixed possible segfault while preparing to write when ASMKERN_INNER is present
    341
    442CLRadeonExtender 0.1.7:
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