Changeset 4793 in CLRX


Ignore:
Timestamp:
Jul 17, 2019, 8:32:47 AM (5 months ago)
Author:
matszpk
Message:

CLRadeonExtender: GCNDisasm: Add missing 1/(2*PI) to literals for GFX10. GCNAsm: Add testcases for GFX10.

Location:
CLRadeonExtender/trunk
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/amdasm/GCNAsmHelpers.cpp

    r4792 r4793  
    12771277            operand.range = {0, 0};
    12781278           
    1279             auto regNameTblEnd = (arch & ARCH_GCN_1_4) ?
     1279            auto regNameTblEnd = (arch & ARCH_GCN_1_4_5) ?
    12801280                        ssourceNamesGCN14Tbl + ssourceNamesGCN14TblSize :
    12811281                        ssourceNamesTbl + ssourceNamesTblSize;
    12821282            auto regNameIt = binaryMapFind(
    1283                     (arch & ARCH_GCN_1_4) ? ssourceNamesGCN14Tbl : ssourceNamesTbl,
     1283                    (arch & ARCH_GCN_1_4_5) ? ssourceNamesGCN14Tbl : ssourceNamesTbl,
    12841284                    regNameTblEnd, regName, CStringLess());
    12851285           
  • CLRadeonExtender/trunk/amdasm/GCNDisasmDecode.cpp

    r4786 r4793  
    307307    {
    308308        case 248:
    309             if (isGCN12)
     309            if (isGCN12 || isGCN15)
    310310            {
    311311                // 1/(2*PI)
  • CLRadeonExtender/trunk/tests/amdasm/GCNAsmOpc15.cpp

    r4792 r4793  
    3939    { "    s_add_u32  ttmp12, s4, s61", 0x80783d04U, 0, false, true, "" },
    4040    { "    s_add_u32  ttmp15, s4, s61", 0x807b3d04U, 0, false, true, "" },
     41    { "s_add_u32 ttmp16, s4, s61", 0x807b3d04U, 0, false, false,
     42        "test.s:1:11: Error: TTMPRegister number out of range (0-15)\n" },
    4143    { "    s_add_u32  tba_lo, s4, s61", 0, 0, false, false,
    4244        "test.s:1:16: Error: Expected 1 scalar register\n" },
     
    4749    { "    s_add_u32  tma_hi, s4, s61", 0, 0, false, false,
    4850        "test.s:1:16: Error: Expected 1 scalar register\n" },
     51    { "s_add_u32 s21, shared_base, s61\n", 0x80153debU, 0, false, true, "" },
     52    { "s_add_u32 s21, src_shared_base, s61\n", 0x80153debU, 0, false, true, "" },
     53    { "s_add_u32 s21, shared_limit, s61\n", 0x80153decU, 0, false, true, "" },
     54    { "s_add_u32 s21, src_shared_limit, s61\n", 0x80153decU, 0, false, true, "" },
     55    { "s_add_u32 s21, private_base, s61\n", 0x80153dedU, 0, false, true, "" },
     56    { "s_add_u32 s21, src_private_base, s61\n", 0x80153dedU, 0, false, true, "" },
     57    { "s_add_u32 s21, private_limit, s61\n", 0x80153deeU, 0, false, true, "" },
     58    { "s_add_u32 s21, src_private_limit, s61\n", 0x80153deeU, 0, false, true, "" },
     59    { "s_add_u32 s21, pops_exiting_wave_id, s61\n", 0x80153defU, 0, false, true, "" },
     60    { "s_add_u32 s21, src_pops_exiting_wave_id, s61\n", 0x80153defU, 0, false, true, "" },
     61    { "s_add_u32 s21, execz, s61\n", 0x80153dfcU, 0, false, true, "" },
     62    { "s_add_u32 s21, src_execz, s61\n", 0x80153dfcU, 0, false, true, "" },
     63    { "s_add_u32 s21, vccz, s61\n", 0x80153dfbU, 0, false, true, "" },
     64    { "s_add_u32 s21, src_vccz, s61\n", 0x80153dfbU, 0, false, true, "" },
     65    { "s_add_u32 s21, scc, s61\n", 0x80153dfdU, 0, false, true, "" },
     66    { "s_add_u32 s21, src_scc, s61\n", 0x80153dfdU, 0, false, true, "" },
     67    /* register's symbols */
     68    { "zx=%s[20:23]; ss=%s4; b=%s[57:67];s_add_u32  zx[1], ss, b[4]",
     69            0x80153d04U, 0, false, true, "" },
     70    { "xv=2; zx=%s[xv+18:xv+19]; ss=%s[xv+2]; b=%s[xv+55:xv+65];"
     71        "s_add_u32  zx[1], ss, b[4]", 0x80153d04U, 0, false, true, "" },
     72    { "zx=%s[20:23]; ss=%execz; b=%s[57:67];s_add_u32  zx[1], ss, b[4]",
     73            0x80153dfcU, 0, false, true, "" },
     74    /* literals */
     75    { "    s_add_u32  s21, s4, 0x2a", 0x8015aa04U, 0, false, true, "" },
     76    { "    s_add_u32  s21, s4, -7", 0x8015c704U, 0, false, true, "" },
     77    { "    s_add_u32  s21, s4, lit(-7)", 0x8015ff04U, 0xfffffff9, true, true, "" },
     78    { "    s_add_u32_e64  s21, s4, -7", 0x8015ff04U, 0xfffffff9, true, true, "" },
     79    { "    s_add_u32  s21, s4, lit(0)", 0x8015ff04U, 0x0, true, true, "" },
     80    { "    s_add_u32  s21, s4, lit(32)", 0x8015ff04U, 0x20, true, true, "" },
     81    { "    s_add_u32_e64 s21, s4, 32", 0x8015ff04U, 0x20, true, true, "" },
     82    { "    s_add_u32_e64 s21, 32, s4", 0x801504ffU, 0x20, true, true, "" },
     83    { "    s_add_u32  s21, s4, lit  (  32  )  ", 0x8015ff04U, 0x20, true, true, "" },
     84    { "    s_add_u32  s21, s4, LiT  (  32  )  ", 0x8015ff04U, 0x20, true, true, "" },
     85    { "    s_add_u32  s21, s4, lit(0.0)", 0x8015ff04U, 0x0, true, true, "" },
     86    { "    s_add_u32  s21, s4, lit(-.5)", 0x8015ff04U, 0xbf000000, true, true, "" },
     87    { "    s_add_u32_e64  s21, s4, -.5", 0x8015ff04U, 0xbf000000, true, true, "" },
     88    { "    s_add_u32  s21, s4, lit(2.0)", 0x8015ff04U, 0x40000000, true, true, "" },
     89    { "    s_add_u32  s21, s4, lit  ( 2.0 )", 0x8015ff04U, 0x40000000, true, true, "" },
     90    { "    s_add_u32_e64  s21, s4, 2.0", 0x8015ff04U, 0x40000000, true, true, "" },
     91    { "    s_add_u32  s21, s4, 1.", 0x8015f204U, 0, false, true, "" },
     92    { "    s_add_u32  s21, s4, -1.", 0x8015f304U, 0, false, true, "" },
     93    { "    s_add_u32  s21, s4, 2.", 0x8015f404U, 0, false, true, "" },
     94    { "    s_add_u32  s21, s4, -2.", 0x8015f504U, 0, false, true, "" },
     95    { "    s_add_u32  s21, s4, 4.", 0x8015f604U, 0, false, true, "" },
     96    { "    s_add_u32  s21, s4, -4.", 0x8015f704U, 0, false, true, "" },
     97    { "    s_add_u32  s21, s4, 1234", 0x8015ff04U, 1234, true, true, "" },
     98    { "    s_add_u32  s21, 1234, s4", 0x801504ffU, 1234, true, true, "" },
     99    { "    s_add_u32  s21, s4, -4.5", 0x8015ff04U, 0xc0900000U, true, true, "" },
     100    { "    s_add_u32  s21, s4, -4.5s", 0x8015ff04U, 0xc0900000U, true, true, "" },
     101    { "    s_add_u32  s21, s4, -4.5h", 0x8015ff04U, 0xc480U, true, true, "" },
     102    { "    s_add_u32  s21, s4, 3e-7", 0x8015ff04U, 0x34a10fb0U, true, true, "" },
     103    /* 64-bit registers and literals */
     104    { "    s_xor_b64 s[22:23], s[4:5], s[62:63]\n", 0x89963e04U, 0, false, true, "" },
     105    { "s1=22; s2=4;s3=62;s_xor_b64 s[s1:s1+1], s[s2:s2+1], s[s3:s3+1]\n",
     106        0x89963e04U, 0, false, true, "" },
     107    { "    s_xor_b64 vcc, s[4:5], s[62:63]\n", 0x89ea3e04U, 0, false, true, "" },
     108    { "    s_xor_b64 vcc[0:1], s[4:5], s[62:63]\n", 0x89ea3e04U, 0, false, true, "" },
     109    { "    s_xor_b64 s[22:23], 1.0, s[62:63]\n", 0x89963ef2U, 0, false, true, "" },
     110    { "    s_xor_b64 s[22:23], vccz, s[62:63]\n", 0x89963efbU, 0, false, true, "" },
     111    { "    s_xor_b64 s[22:23], execz, s[62:63]\n", 0x89963efcU, 0, false, true, "" },
     112    { "    s_xor_b64 s[22:23], scc, s[62:63]\n", 0x89963efdU, 0, false, true, "" },
    49113    { nullptr, 0, 0, false, false, 0 }
    50114};
    51 
  • CLRadeonExtender/trunk/tests/amdasm/GCNDisasmOpc15.cpp

    r4786 r4793  
    4848    { 0x80157a04U, 0, false, "        s_add_u32       s21, s4, ttmp14\n" },
    4949    { 0x80157b04U, 0, false, "        s_add_u32       s21, s4, ttmp15\n" },
     50    { 0x80153df8U, 0, false, "        s_add_u32       s21, 0.15915494, s61\n" },
    5051    { 0x80157c04U, 0, false, "        s_add_u32       s21, s4, m0\n" },
    5152    { 0x80157e04U, 0, false, "        s_add_u32       s21, s4, exec_lo\n" },
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