Changeset 4794 in CLRX


Ignore:
Timestamp:
Jul 17, 2019, 9:27:40 AM (5 months ago)
Author:
matszpk
Message:

CLRadeonExtender: GCNAsm: Changes for GFX10 in GCNAsmHelpers. Next testcases for GFX10.

Location:
CLRadeonExtender/trunk
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/amdasm/GCNAsmHelpers.cpp

    r4793 r4794  
    26612661    if (needImm)
    26622662        ASM_FAIL_BY_ERROR(instrPlace, "Literal with SDWA or DPP word is illegal")
    2663     if ((arch & ARCH_GCN_1_4)==0 && !src0Op.range.isVGPR())
     2663    if ((arch & ARCH_GCN_1_4_5)==0 && !src0Op.range.isVGPR())
    26642664        ASM_FAIL_BY_ERROR(instrPlace, "SRC0 must be a vector register with "
    26652665                    "SDWA or DPP word")
    2666     if ((arch & ARCH_GCN_1_4)!=0 && extraMods.needDPP && !src0Op.range.isVGPR())
     2666    if ((arch & ARCH_GCN_1_4_5)!=0 && extraMods.needDPP && !src0Op.range.isVGPR())
    26672667        ASM_FAIL_BY_ERROR(instrPlace, "SRC0 must be a vector register with DPP word")
    26682668    if (vop3)
  • CLRadeonExtender/trunk/tests/amdasm/GCNAsmOpc15.cpp

    r4793 r4794  
    2323const GCNAsmOpcodeCase encGCN15OpcodeCases[] =
    2424{
     25    { "    s_add_u32  flat_scratch_lo, s4, s61", 0, 0, false, false,
     26        "test.s:1:16: Error: Expected 1 scalar register\n" },
     27    { "    s_add_u32  flat_scratch_hi, s4, s61", 0, 0, false, false,
     28        "test.s:1:16: Error: Expected 1 scalar register\n" },
     29    { "    s_add_u32  xnack_mask_lo, s4, s61", 0, 0, false, false,
     30        "test.s:1:16: Error: Expected 1 scalar register\n" },
     31    { "    s_add_u32  xnack_mask_hi, s4, s61", 0, 0, false, false,
     32        "test.s:1:16: Error: Expected 1 scalar register\n" },
    2533    { "        s_add_u32       s21, s4, s61\n", 0x80153d04U, 0, false, true, "" },
    2634    { "        s_add_u32       s21, s4, s100\n", 0x80156404U, 0, false, true, "" },
     
    3240    { "        s_add_u32       s21, s4, vcc_lo\n", 0x80156a04U, 0, false, true, "" },
    3341    { "        s_add_u32       s21, s4, vcc_hi\n", 0x80156b04U, 0, false, true, "" },
     42    { "    s_add_u32  s21, 0.15915494, s61", 0x80153df8U, 0, false, true, "" },
     43    { "vval=%0.15915494; s_add_u32  s21, vval, s61",
     44        0x80153df8U, 0, false, true, "" },
     45    { "        s_add_u32       s21, s4, null\n", 0x80157d04U, 0, false, true, "" },
     46    { "        s_add_u32       s21, null, s61\n", 0x80153d7dU, 0, false, true, "" },
     47    { "        s_add_u32       null, s4, s61\n", 0x807d3d04U, 0, false, true, "" },
    3448    { "    s_add_u32  vcc[1:1], s4, s61", 0x806b3d04U, 0, false, true, "" },
    3549    { "    s_add_u32  vcc[1], s4, s61", 0x806b3d04U, 0, false, true, "" },
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