Changeset 4811 in CLRX


Ignore:
Timestamp:
Jul 19, 2019, 6:59:15 PM (3 months ago)
Author:
matszpk
Message:

CLRadeonExtender: GCNAsm: Add VOP DPP8 testcases.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/tests/amdasm/GCNAsmOpc15.cpp

    r4810 r4811  
    11241124        0x0734d6faU, 0x140be, true, true, "" },
    11251125    /* VOP DPP8 */
    1126     { "v_add_f32       v154, v190, v107 " "dpp8:[1,7,2,5,6,3,6,4]\n",
     1126    { "v_add_f32       v154, v190, v107 dpp8:[1,7,2,5,6,3,6,4]\n",
    11271127        0x0734d6e9U, 0x99eab9be, true, true, "" },
     1128    { "v_add_f32_dpp   v154, v190, v107 dpp8:[1,7,2,5,6,3,6,4]\n",
     1129        0x0734d6e9U, 0x99eab9be, true, true, "" },
     1130    { "v_add_f32       v154, v190, v107 dpp8 :  [ 1 ,  7, 2, 5, 6, 3 , 6 , 4  ]  \n",
     1131        0x0734d6e9U, 0x99eab9be, true, true, "" },
     1132    { "a=6; v_add_f32       v154, v190, v107 dpp8:[1,7,2,5,a,a/2,a,4]\n",
     1133        0x0734d6e9U, 0x99eab9be, true, true, "" },
     1134    { "v_add_f32       v154, v190, v107 dpp8:[1,7,2,5,6,3,6,4] fi\n",
     1135        0x0734d6eaU, 0x99eab9be, true, true, "" },
     1136    { "v_add_f32       v154, v190, v107  fi:1   dpp8:[1,7,2,5,6,3,6,4]\n",
     1137        0x0734d6eaU, 0x99eab9be, true, true, "" },
     1138    { "v_add_f32       v154, v190, v107 dpp8:[1,7,2,13,6,3,6,4]\n",
     1139        0x0734d6e9U, 0x99eab9be, true, true,
     1140        "test.s:1:46: Warning: Value 0xd truncated to 0x5\n" },
     1141    { "v_add_f32       v154, v190, v107 dpp8:[1,7,2,5,6,3,6,0x1114]\n",
     1142        0x0734d6e9U, 0x99eab9be, true, true,
     1143        "test.s:1:54: Warning: Value 0x1114 truncated to 0x4\n" },
     1144    { "v_add_f32       v154, v190, v107 dpp8:[0,7,0,0,0,0,0,0]\n",
     1145        0x0734d6e9U, 0x38be, true, true, "" },
     1146    { "v_add_f32       v154, v190, v107 dpp8:[0,0,7,0,0,0,0,0]\n",
     1147        0x0734d6e9U, 0x1c0be, true, true, "" },
     1148    { "v_add_f32       v154, v190, v107 dpp8:[0,0,0,7,0,0,0,0]\n",
     1149        0x0734d6e9U, 0xe00be, true, true, "" },
     1150    { "v_add_f32       v154, v190, v107 dpp8:[0,0,0,0,0,0,7,0]\n",
     1151        0x0734d6e9U, 0x1c0000be, true, true, "" },
     1152    { "v_add_f32       v154, v190, v107 dpp8:[0,0,0,0,0,0,0,7]\n",
     1153        0x0734d6e9U, 0xe00000be, true, true, "" },
     1154    /* VOP DPP8 errors */
     1155    { "v_add_f32  v154, v190, abs(v107) dpp8:[1,7,2,5,6,3,6,4]\n", 0, 0, false, false,
     1156        "test.s:1:1: Error: ABS and NEG modifiers is unavailable for DPP8 word\n" },
     1157    { "v_add_f32  v154, v190, -v107 dpp8:[1,7,2,5,6,3,6,4]\n", 0, 0, false, false,
     1158        "test.s:1:1: Error: ABS and NEG modifiers is unavailable for DPP8 word\n" },
     1159    { "v_add_f32  v154, abs(v190), v107 dpp8:[1,7,2,5,6,3,6,4]\n", 0, 0, false, false,
     1160        "test.s:1:1: Error: ABS and NEG modifiers is unavailable for DPP8 word\n" },
     1161    { "v_add_f32  v154, -v190, v107 dpp8:[1,7,2,5,6,3,6,4]\n", 0, 0, false, false,
     1162        "test.s:1:1: Error: ABS and NEG modifiers is unavailable for DPP8 word\n" },
     1163    { "v_add_f32       v154, s10, v107 dpp8:[1,7,2,5,6,3,6,4]\n", 0, 0, false, false,
     1164        "test.s:1:1: Error: SRC0 must be a vector register with DPP word\n" },
     1165    { "v_add_f32 v154, v190, sext(v107) dpp8:[1,7,2,5,6,3,6,4]\n", 0, 0, false, false,
     1166        "test.s:1:1: Error: SEXT modifiers is unavailable for DPP word\n" },
     1167    { "v_add_f32 v154, v190, v107 row_shl:3 dpp8:[1,7,2,5,6,3,6,4]\n", 0, 0, false, false,
     1168        "test.s:1:28: Error: Mixing modifiers from different encodings is illegal\n" },
    11281169    { nullptr, 0, 0, false, false, 0 }
    11291170};
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