Changeset 4831 in CLRX
- Timestamp:
- Jul 24, 2019, 9:22:18 AM (5 months ago)
- Location:
- CLRadeonExtender/trunk
- Files:
-
- 9 edited
-
amdasm/GCNAsmEncode1.cpp (modified) (2 diffs)
-
amdasm/GCNDisasm.cpp (modified) (1 diff)
-
amdasm/GCNInstructions.cpp (modified) (36 diffs)
-
amdasm/GCNInternals.h (modified) (1 diff)
-
tests/amdasm/GCNAsmOpc11.cpp (modified) (1 diff)
-
tests/amdasm/GCNAsmOpc15.cpp (modified) (1 diff)
-
tests/amdasm/GCNDisasmOpc11.cpp (modified) (1 diff)
-
tests/amdasm/GCNDisasmOpc12.cpp (modified) (1 diff)
-
tests/amdasm/GCNDisasmOpc15.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
CLRadeonExtender/trunk/amdasm/GCNAsmEncode1.cpp
r4829 r4831 1325 1325 bool good = true; 1326 1326 const GCNInsnMode mode1 = (gcnInsn.mode & GCN_MASK1); 1327 const GCNInsnMode mode2 = (gcnInsn.mode & GCN_ MASK2);1327 const GCNInsnMode mode2 = (gcnInsn.mode & GCN_LITMASK); 1328 1328 const bool isGCN12 = (arch & ARCH_GCN_1_2_4_5)!=0; 1329 1329 const bool isGCN14 = (arch & ARCH_GCN_1_4_5)!=0; … … 1615 1615 bool good = true; 1616 1616 const GCNInsnMode mode1 = (gcnInsn.mode & GCN_MASK1); 1617 const GCNInsnMode mode2 = (gcnInsn.mode & GCN_ MASK2);1617 const GCNInsnMode mode2 = (gcnInsn.mode & GCN_LITMASK); 1618 1618 const bool isGCN12 = (arch & ARCH_GCN_1_2_4_5)!=0; 1619 1619 const bool isGCN14 = (arch & ARCH_GCN_1_4_5)!=0; -
CLRadeonExtender/trunk/amdasm/GCNDisasm.cpp
r4786 r4831 1006 1006 const FloatLitType displayFloatLits = 1007 1007 ((disassembler.getFlags()&DISASM_FLOATLITS) != 0) ? 1008 (((gcnInsn->mode & GCN_ MASK2) == GCN_FLOATLIT) ? FLTLIT_F32 :1009 ((gcnInsn->mode & GCN_ MASK2) == GCN_F16LIT) ? FLTLIT_F16 :1008 (((gcnInsn->mode & GCN_LITMASK) == GCN_FLOATLIT) ? FLTLIT_F32 : 1009 ((gcnInsn->mode & GCN_LITMASK) == GCN_F16LIT) ? FLTLIT_F16 : 1010 1010 FLTLIT_NONE) : FLTLIT_NONE; 1011 1011 -
CLRadeonExtender/trunk/amdasm/GCNInstructions.cpp
r4798 r4831 461 461 { "v_dot2c_f32_f16", GCNENC_VOP2, GCN_F16LIT, 2, ARCH_NAVI_DL }, 462 462 { "v_add_f32", GCNENC_VOP2, GCN_FLOATLIT, 3, ARCH_GCN_1_0_1_5 }, 463 { "v_add_f32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 259, ARCH_GCN_1_0_1_5 }, 463 { "v_add_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP2_DS01, 464 259, ARCH_GCN_1_0_1_5 }, 464 465 { "v_sub_f32", GCNENC_VOP2, GCN_FLOATLIT, 4, ARCH_GCN_1_0_1_5 }, 465 { "v_sub_f32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 260, ARCH_GCN_1_0_1_5 }, 466 { "v_sub_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP2_DS01, 467 260, ARCH_GCN_1_0_1_5 }, 466 468 { "v_subrev_f32", GCNENC_VOP2, GCN_FLOATLIT, 5, ARCH_GCN_1_0_1_5 }, 467 { "v_subrev_f32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 261, ARCH_GCN_1_0_1_5 }, 469 { "v_subrev_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP2_DS01, 470 261, ARCH_GCN_1_0_1_5 }, 468 471 { "v_mac_legacy_f32", GCNENC_VOP2, GCN_FLOATLIT, 6, ARCH_GCN_1_0_1_5 }, 469 { "v_mac_legacy_f32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 262, ARCH_GCN_1_0_1_5 }, 472 { "v_mac_legacy_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP2_DS01, 473 262, ARCH_GCN_1_0_1_5 }, 470 474 { "v_mul_legacy_f32", GCNENC_VOP2, GCN_FLOATLIT, 7, ARCH_GCN_1_0_1_5 }, 471 { "v_mul_legacy_f32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 263, ARCH_GCN_1_0_1_5 }, 475 { "v_mul_legacy_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP2_DS01, 476 263, ARCH_GCN_1_0_1_5 }, 472 477 { "v_mul_f32", GCNENC_VOP2, GCN_FLOATLIT, 8, ARCH_GCN_1_0_1_5 }, 473 { "v_mul_f32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 264, ARCH_GCN_1_0_1_5 }, 478 { "v_mul_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP2_DS01, 479 264, ARCH_GCN_1_0_1_5 }, 474 480 { "v_mul_i32_i24", GCNENC_VOP2, GCN_STDMODE, 9, ARCH_GCN_1_0_1_5 }, 475 481 { "v_mul_i32_i24", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 265, ARCH_GCN_1_0_1_5 }, … … 486 492 { "v_max_legacy_f32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 270, ARCH_GCN_1_0_1 }, 487 493 { "v_min_f32", GCNENC_VOP2, GCN_FLOATLIT, 15, ARCH_GCN_1_0_1_5 }, 488 { "v_min_f32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 271, ARCH_GCN_1_0_1_5 }, 494 { "v_min_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP2_DS01, 495 271, ARCH_GCN_1_0_1_5 }, 489 496 { "v_max_f32", GCNENC_VOP2, GCN_FLOATLIT, 16, ARCH_GCN_1_0_1_5 }, 490 { "v_max_f32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 272, ARCH_GCN_1_0_1_5 }, 497 { "v_max_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP2_DS01, 498 272, ARCH_GCN_1_0_1_5 }, 491 499 { "v_min_i32", GCNENC_VOP2, GCN_STDMODE, 17, ARCH_GCN_1_0_1_5 }, 492 500 { "v_min_i32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 273, ARCH_GCN_1_0_1_5 }, … … 520 528 { "v_bfm_b32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 286, ARCH_GCN_1_0_1 }, 521 529 { "v_mac_f32", GCNENC_VOP2, GCN_FLOATLIT, 31, ARCH_GCN_1_0_1_5 }, 522 { "v_mac_f32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 287, ARCH_GCN_1_0_1_5 }, 530 { "v_mac_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP2_DS01, 531 287, ARCH_GCN_1_0_1_5 }, 523 532 { "v_madmk_f32", GCNENC_VOP2, GCN_FLOATLIT|GCN_ARG1_IMM,32, ARCH_GCN_1_0_1_5 }, 524 533 { "v_madmk_f32", GCNENC_VOP3A, GCN_VOP3_VOP2|GCN_ARG1_IMM, 288, ARCH_GCN_1_0_1_5 }, … … 570 579 { "v_cvt_pknorm_u16_f32",GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 302, ARCH_GCN_1_0_1 }, 571 580 { "v_cvt_pkrtz_f16_f32", GCNENC_VOP2, GCN_FLOATLIT, 47, ARCH_GCN_1_0_1_5 }, 572 { "v_cvt_pkrtz_f16_f32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 303, ARCH_GCN_1_0_1_5 }, 581 { "v_cvt_pkrtz_f16_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP2_DS01, 582 303, ARCH_GCN_1_0_1_5 }, 573 583 { "v_cvt_pk_u16_u32", GCNENC_VOP2, GCN_STDMODE, 48, ARCH_GCN_1_0_1 }, 574 584 { "v_cvt_pk_u16_u32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 304, ARCH_GCN_1_0_1 }, … … 710 720 { "v_xnor_b32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 317, ARCH_VEGA20 }, 711 721 { "v_fmac_f32", GCNENC_VOP2, GCN_FLOATLIT|GCN_VOP_NOSDWA, 43, ARCH_GCN_1_5 }, 712 { "v_fmac_f32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 299, ARCH_GCN_1_5 }, 722 { "v_fmac_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP2_DS01, 723 299, ARCH_GCN_1_5 }, 713 724 { "v_fmamk_f32", GCNENC_VOP2, GCN_FLOATLIT|GCN_ARG1_IMM,44, ARCH_GCN_1_0_1_5 }, 714 725 { "v_fmamk_f32", GCNENC_VOP3A, GCN_VOP3_VOP2|GCN_ARG1_IMM, 300, ARCH_GCN_1_0_1_5 }, … … 716 727 { "v_fmaak_f32", GCNENC_VOP3A, GCN_VOP3_VOP2|GCN_ARG2_IMM, 301, ARCH_GCN_1_0_1_5 }, 717 728 { "v_add_f16", GCNENC_VOP2, GCN_F16LIT, 50, ARCH_GCN_1_5 }, 718 { "v_add_f16", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 306, ARCH_GCN_1_5 }, 729 { "v_add_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP2_DS01, 730 306, ARCH_GCN_1_5 }, 719 731 { "v_sub_f16", GCNENC_VOP2, GCN_F16LIT, 51, ARCH_GCN_1_5 }, 720 { "v_sub_f16", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 307, ARCH_GCN_1_5 }, 732 { "v_sub_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP2_DS01, 733 307, ARCH_GCN_1_5 }, 721 734 { "v_subrev_f16", GCNENC_VOP2, GCN_F16LIT, 52, ARCH_GCN_1_5 }, 722 { "v_subrev_f16", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 308, ARCH_GCN_1_5 }, 735 { "v_subrev_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP2_DS01, 736 308, ARCH_GCN_1_5 }, 723 737 { "v_mul_f16", GCNENC_VOP2, GCN_F16LIT, 53, ARCH_GCN_1_5 }, 724 { "v_mul_f16", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 309, ARCH_GCN_1_5 }, 738 { "v_mul_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP2_DS01, 739 309, ARCH_GCN_1_5 }, 725 740 { "v_fmac_f16", GCNENC_VOP2, GCN_F16LIT|GCN_VOP_NOSDWA, 54, ARCH_GCN_1_5 }, 726 { "v_fmac_f16", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 310, ARCH_GCN_1_5 }, 741 { "v_fmac_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP2_DS01, 742 310, ARCH_GCN_1_5 }, 727 743 { "v_fmamk_f16", GCNENC_VOP2, GCN_F16LIT|GCN_ARG1_IMM,55, ARCH_GCN_1_5 }, 728 744 { "v_fmamk_f16", GCNENC_VOP3A, GCN_VOP3_VOP2|GCN_ARG1_IMM, 311, ARCH_GCN_1_5 }, … … 730 746 { "v_fmaak_f16", GCNENC_VOP3A, GCN_VOP3_VOP2|GCN_ARG2_IMM, 312, ARCH_GCN_1_5 }, 731 747 { "v_max_f16", GCNENC_VOP2, GCN_F16LIT, 57, ARCH_GCN_1_5 }, 732 { "v_max_f16", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 313, ARCH_GCN_1_5 }, 748 { "v_max_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP2_DS01, 749 313, ARCH_GCN_1_5 }, 733 750 { "v_min_f16", GCNENC_VOP2, GCN_F16LIT, 58, ARCH_GCN_1_5 }, 734 { "v_min_f16", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 314, ARCH_GCN_1_5 }, 751 { "v_min_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP2_DS01, 752 314, ARCH_GCN_1_5 }, 735 753 { "v_ldexp_f16", GCNENC_VOP2, GCN_F16LIT, 59, ARCH_GCN_1_5 }, 736 { "v_ldexp_f16", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01, 315, ARCH_GCN_1_5 }, 754 { "v_ldexp_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP2_DS01, 755 315, ARCH_GCN_1_5 }, 737 756 { "v_pk_fmac_f16", GCNENC_VOP2, GCN_F16LIT, 60, ARCH_GCN_1_5 }, 738 757 { "v_nop", GCNENC_VOP1, GCN_VOP_ARG_NONE, 0, ARCH_GCN_ALL }, … … 763 782 { "v_cvt_u32_f32", GCNENC_VOP1, GCN_FLOATLIT, 7, ARCH_GCN_ALL }, 764 783 { "v_cvt_u32_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 327, ARCH_GCN_1_2_4 }, 765 { "v_cvt_u32_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 391, ARCH_GCN_1_0_1_5 }, 784 { "v_cvt_u32_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 785 391, ARCH_GCN_1_0_1_5 }, 766 786 { "v_cvt_i32_f32", GCNENC_VOP1, GCN_FLOATLIT, 8, ARCH_GCN_ALL }, 767 787 { "v_cvt_i32_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 328, ARCH_GCN_1_2_4 }, 768 { "v_cvt_i32_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 392, ARCH_GCN_1_0_1_5 }, 788 { "v_cvt_i32_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 789 392, ARCH_GCN_1_0_1_5 }, 769 790 { "v_mov_fed_b32", GCNENC_VOP1, GCN_STDMODE, 9, ARCH_GCN_ALL }, 770 791 { "v_mov_fed_b32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 329, ARCH_GCN_1_2_4 }, … … 772 793 { "v_cvt_f16_f32", GCNENC_VOP1, GCN_FLOATLIT, 10, ARCH_GCN_ALL }, 773 794 { "v_cvt_f16_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 330, ARCH_GCN_1_2_4 }, 774 { "v_cvt_f16_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 394, ARCH_GCN_1_0_1_5 }, 775 { "v_cvt_f32_f16", GCNENC_VOP1, GCN_STDMODE, 11, ARCH_GCN_ALL }, 795 { "v_cvt_f16_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 796 394, ARCH_GCN_1_0_1_5 }, 797 { "v_cvt_f32_f16", GCNENC_VOP1, GCN_F16LIT, 11, ARCH_GCN_ALL }, 776 798 { "v_cvt_f32_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 331, ARCH_GCN_1_2_4 }, 777 { "v_cvt_f32_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 395, ARCH_GCN_1_0_1_5 }, 799 { "v_cvt_f32_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 800 395, ARCH_GCN_1_0_1_5 }, 778 801 { "v_cvt_rpi_i32_f32", GCNENC_VOP1, GCN_FLOATLIT, 12, ARCH_GCN_ALL }, 779 802 { "v_cvt_rpi_i32_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 332, ARCH_GCN_1_2_4 }, … … 792 815 16, ARCH_GCN_ALL }, 793 816 { "v_cvt_f64_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0|GCN_REG_DST_64,336, ARCH_GCN_1_2_4 }, 794 { "v_cvt_f64_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0|GCN_ REG_DST_64,817 { "v_cvt_f64_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0|GCN_FLOATLIT|GCN_REG_DST_64, 795 818 400, ARCH_GCN_1_0_1_5 }, 796 819 { "v_cvt_f32_ubyte0", GCNENC_VOP1, GCN_STDMODE, 17, ARCH_GCN_ALL }, … … 829 852 { "v_pipeflush", GCNENC_VOP3A, GCN_VOP_ARG_NONE|GCN_VOP3_VOP1, 411, ARCH_GCN_1_5 }, 830 853 { "v_fract_f32", GCNENC_VOP1, GCN_FLOATLIT, 32, ARCH_GCN_1_0_1_5 }, 831 { "v_fract_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 416, ARCH_GCN_1_0_1_5 }, 854 { "v_fract_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 855 416, ARCH_GCN_1_0_1_5 }, 832 856 { "v_trunc_f32", GCNENC_VOP1, GCN_FLOATLIT, 33, ARCH_GCN_1_0_1_5 }, 833 { "v_trunc_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 417, ARCH_GCN_1_0_1_5 }, 857 { "v_trunc_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 858 417, ARCH_GCN_1_0_1_5 }, 834 859 { "v_ceil_f32", GCNENC_VOP1, GCN_FLOATLIT, 34, ARCH_GCN_1_0_1_5 }, 835 { "v_ceil_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 418, ARCH_GCN_1_0_1_5 }, 860 { "v_ceil_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 861 418, ARCH_GCN_1_0_1_5 }, 836 862 { "v_rndne_f32", GCNENC_VOP1, GCN_FLOATLIT, 35, ARCH_GCN_1_0_1_5 }, 837 { "v_rndne_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 419, ARCH_GCN_1_0_1_5 }, 863 { "v_rndne_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 864 419, ARCH_GCN_1_0_1_5 }, 838 865 { "v_floor_f32", GCNENC_VOP1, GCN_FLOATLIT, 36, ARCH_GCN_1_0_1_5 }, 839 { "v_floor_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 420, ARCH_GCN_1_0_1_5 }, 866 { "v_floor_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 867 420, ARCH_GCN_1_0_1_5 }, 840 868 { "v_exp_f32", GCNENC_VOP1, GCN_FLOATLIT, 37, ARCH_GCN_1_0_1_5 }, 841 { "v_exp_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 421, ARCH_GCN_1_0_1_5 }, 869 { "v_exp_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 870 421, ARCH_GCN_1_0_1_5 }, 842 871 { "v_log_clamp_f32", GCNENC_VOP1, GCN_FLOATLIT, 38, ARCH_GCN_1_0_1 }, 843 872 { "v_log_clamp_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 422, ARCH_GCN_1_0_1 }, 844 873 { "v_log_f32", GCNENC_VOP1, GCN_FLOATLIT, 39, ARCH_GCN_1_0_1_5 }, 845 { "v_log_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 423, ARCH_GCN_1_0_1_5 }, 874 { "v_log_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 875 423, ARCH_GCN_1_0_1_5 }, 846 876 { "v_rcp_clamp_f32", GCNENC_VOP1, GCN_FLOATLIT, 40, ARCH_GCN_1_0_1 }, 847 877 { "v_rcp_clamp_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 424, ARCH_GCN_1_0_1 }, … … 849 879 { "v_rcp_legacy_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 425, ARCH_GCN_1_0_1 }, 850 880 { "v_rcp_f32", GCNENC_VOP1, GCN_FLOATLIT, 42, ARCH_GCN_1_0_1_5 }, 851 { "v_rcp_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 426, ARCH_GCN_1_0_1_5 }, 881 { "v_rcp_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 882 426, ARCH_GCN_1_0_1_5 }, 852 883 { "v_rcp_iflag_f32", GCNENC_VOP1, GCN_FLOATLIT, 43, ARCH_GCN_1_0_1_5 }, 853 { "v_rcp_iflag_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 427, ARCH_GCN_1_0_1_5 }, 884 { "v_rcp_iflag_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 885 427, ARCH_GCN_1_0_1_5 }, 854 886 { "v_rsq_clamp_f32", GCNENC_VOP1, GCN_FLOATLIT, 44, ARCH_GCN_1_0_1 }, 855 887 { "v_rsq_clamp_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 428, ARCH_GCN_1_0_1 }, … … 857 889 { "v_rsq_legacy_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 429, ARCH_GCN_1_0_1 }, 858 890 { "v_rsq_f32", GCNENC_VOP1, GCN_FLOATLIT, 46, ARCH_GCN_1_0_1_5 }, 859 { "v_rsq_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 430, ARCH_GCN_1_0_1_5 }, 891 { "v_rsq_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 892 430, ARCH_GCN_1_0_1_5 }, 860 893 { "v_rcp_f64", GCNENC_VOP1, GCN_REG_DS0_64, 47, ARCH_GCN_1_0_1_5 }, 861 894 { "v_rcp_f64", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0|GCN_REG_DS0_64, … … 869 902 { "v_rsq_clamp_f64", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0|GCN_REG_DS0_64,434, ARCH_GCN_1_0_1 }, 870 903 { "v_sqrt_f32", GCNENC_VOP1, GCN_FLOATLIT, 51, ARCH_GCN_1_0_1_5 }, 871 { "v_sqrt_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 435, ARCH_GCN_1_0_1_5 }, 904 { "v_sqrt_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 905 435, ARCH_GCN_1_0_1_5 }, 872 906 { "v_sqrt_f64", GCNENC_VOP1, GCN_REG_DS0_64, 52, ARCH_GCN_1_0_1_5 }, 873 907 { "v_sqrt_f64", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0|GCN_REG_DS0_64, 874 908 436, ARCH_GCN_1_0_1_5 }, 875 909 { "v_sin_f32", GCNENC_VOP1, GCN_FLOATLIT, 53, ARCH_GCN_1_0_1_5 }, 876 { "v_sin_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 437, ARCH_GCN_1_0_1_5 }, 910 { "v_sin_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 911 437, ARCH_GCN_1_0_1_5 }, 877 912 { "v_cos_f32", GCNENC_VOP1, GCN_FLOATLIT, 54, ARCH_GCN_1_0_1_5 }, 878 { "v_cos_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 438, ARCH_GCN_1_0_1_5 }, 913 { "v_cos_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 914 438, ARCH_GCN_1_0_1_5 }, 879 915 { "v_not_b32", GCNENC_VOP1, GCN_STDMODE, 55, ARCH_GCN_1_0_1_5 }, 880 916 { "v_not_b32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 439, ARCH_GCN_1_0_1_5 }, … … 897 933 446, ARCH_GCN_1_0_1_5 }, 898 934 { "v_frexp_exp_i32_f32", GCNENC_VOP1, GCN_FLOATLIT, 63, ARCH_GCN_1_0_1_5 }, 899 { "v_frexp_exp_i32_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 447, ARCH_GCN_1_0_1_5 }, 935 { "v_frexp_exp_i32_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 936 447, ARCH_GCN_1_0_1_5 }, 900 937 { "v_frexp_mant_f32", GCNENC_VOP1, GCN_FLOATLIT, 64, ARCH_GCN_1_0_1_5 }, 901 { "v_frexp_mant_f32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 448, ARCH_GCN_1_0_1_5 }, 938 { "v_frexp_mant_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_VOP1_DS0, 939 448, ARCH_GCN_1_0_1_5 }, 902 940 { "v_clrexcp", GCNENC_VOP1, GCN_VOP_ARG_NONE, 65, ARCH_GCN_1_0_1_5 }, 903 941 { "v_clrexcp", GCNENC_VOP3A, GCN_VOP_ARG_NONE|GCN_VOP3_VOP1, … … 1035 1073 { "v_cvt_f16_i16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 465, ARCH_GCN_1_5 }, 1036 1074 { "v_cvt_u16_f16", GCNENC_VOP1, GCN_F16LIT, 82, ARCH_GCN_1_5 }, 1037 { "v_cvt_u16_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 466, ARCH_GCN_1_5 }, 1075 { "v_cvt_u16_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1076 466, ARCH_GCN_1_5 }, 1038 1077 { "v_cvt_i16_f16", GCNENC_VOP1, GCN_F16LIT, 83, ARCH_GCN_1_5 }, 1039 { "v_cvt_i16_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 467, ARCH_GCN_1_5 }, 1078 { "v_cvt_i16_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1079 467, ARCH_GCN_1_5 }, 1040 1080 { "v_rcp_f16", GCNENC_VOP1, GCN_F16LIT, 84, ARCH_GCN_1_5 }, 1041 { "v_rcp_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 468, ARCH_GCN_1_5 }, 1081 { "v_rcp_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1082 468, ARCH_GCN_1_5 }, 1042 1083 { "v_sqrt_f16", GCNENC_VOP1, GCN_F16LIT, 85, ARCH_GCN_1_5 }, 1043 { "v_sqrt_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 469, ARCH_GCN_1_5 }, 1084 { "v_sqrt_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1085 469, ARCH_GCN_1_5 }, 1044 1086 { "v_rsq_f16", GCNENC_VOP1, GCN_F16LIT, 86, ARCH_GCN_1_5 }, 1045 { "v_rsq_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 470, ARCH_GCN_1_5 }, 1087 { "v_rsq_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1088 470, ARCH_GCN_1_5 }, 1046 1089 { "v_log_f16", GCNENC_VOP1, GCN_F16LIT, 87, ARCH_GCN_1_5 }, 1047 { "v_log_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 471, ARCH_GCN_1_5 }, 1090 { "v_log_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1091 471, ARCH_GCN_1_5 }, 1048 1092 { "v_exp_f16", GCNENC_VOP1, GCN_F16LIT, 88, ARCH_GCN_1_5 }, 1049 { "v_exp_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 472, ARCH_GCN_1_5 }, 1093 { "v_exp_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1094 472, ARCH_GCN_1_5 }, 1050 1095 { "v_frexp_mant_f16", GCNENC_VOP1, GCN_F16LIT, 89, ARCH_GCN_1_5 }, 1051 { "v_frexp_mant_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 473, ARCH_GCN_1_5 }, 1096 { "v_frexp_mant_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1097 473, ARCH_GCN_1_5 }, 1052 1098 { "v_frexp_exp_i16_f16", GCNENC_VOP1, GCN_F16LIT, 90, ARCH_GCN_1_5 }, 1053 { "v_frexp_exp_i16_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 474, ARCH_GCN_1_5 }, 1099 { "v_frexp_exp_i16_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1100 474, ARCH_GCN_1_5 }, 1054 1101 { "v_floor_f16", GCNENC_VOP1, GCN_F16LIT, 91, ARCH_GCN_1_5 }, 1055 { "v_floor_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 475, ARCH_GCN_1_5 }, 1102 { "v_floor_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1103 475, ARCH_GCN_1_5 }, 1056 1104 { "v_ceil_f16", GCNENC_VOP1, GCN_F16LIT, 92, ARCH_GCN_1_5 }, 1057 { "v_ceil_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 476, ARCH_GCN_1_5 }, 1105 { "v_ceil_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1106 476, ARCH_GCN_1_5 }, 1058 1107 { "v_trunc_f16", GCNENC_VOP1, GCN_F16LIT, 93, ARCH_GCN_1_5 }, 1059 { "v_trunc_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 477, ARCH_GCN_1_5 }, 1108 { "v_trunc_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1109 477, ARCH_GCN_1_5 }, 1060 1110 { "v_rndne_f16", GCNENC_VOP1, GCN_F16LIT, 94, ARCH_GCN_1_5 }, 1061 { "v_rndne_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 478, ARCH_GCN_1_5 }, 1111 { "v_rndne_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1112 478, ARCH_GCN_1_5 }, 1062 1113 { "v_fract_f16", GCNENC_VOP1, GCN_F16LIT, 95, ARCH_GCN_1_5 }, 1063 { "v_fract_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 479, ARCH_GCN_1_5 }, 1114 { "v_fract_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1115 479, ARCH_GCN_1_5 }, 1064 1116 { "v_sin_f16", GCNENC_VOP1, GCN_F16LIT, 96, ARCH_GCN_1_5 }, 1065 { "v_sin_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 480, ARCH_GCN_1_5 }, 1117 { "v_sin_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1118 480, ARCH_GCN_1_5 }, 1066 1119 { "v_cos_f16", GCNENC_VOP1, GCN_F16LIT, 97, ARCH_GCN_1_5 }, 1067 { "v_cos_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 481, ARCH_GCN_1_5 }, 1120 { "v_cos_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1121 481, ARCH_GCN_1_5 }, 1068 1122 { "v_sat_pk_u8_i16", GCNENC_VOP1, GCN_STDMODE, 98, ARCH_GCN_1_5 }, 1069 1123 { "v_sat_pk_u8_i16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 482, ARCH_GCN_1_5 }, 1070 1124 { "v_cvt_norm_i16_f16", GCNENC_VOP1, GCN_F16LIT, 99, ARCH_GCN_1_5 }, 1071 { "v_cvt_norm_i16_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 483, ARCH_GCN_1_5 }, 1125 { "v_cvt_norm_i16_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1126 483, ARCH_GCN_1_5 }, 1072 1127 { "v_cvt_norm_u16_f16", GCNENC_VOP1, GCN_F16LIT, 100, ARCH_GCN_1_5 }, 1073 { "v_cvt_norm_u16_f16", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 484, ARCH_GCN_1_5 }, 1128 { "v_cvt_norm_u16_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_VOP1_DS0, 1129 484, ARCH_GCN_1_5 }, 1074 1130 { "v_swap_b32", GCNENC_VOP1, GCN_STDMODE|GCN_VOP_NODPPSDWA, 101, ARCH_GCN_1_5 }, 1075 1131 { "v_swap_b32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 485, ARCH_GCN_1_5 }, … … 1077 1133 { "v_swaprel_b32", GCNENC_VOP3A, GCN_VOP3_VOP1_DS0, 488, ARCH_GCN_1_5 }, 1078 1134 { "v_cmp_f_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x00, ARCH_GCN_1_0_1_5 }, 1079 { "v_cmp_f_f32", GCNENC_VOP3A, GCN_STDMODE, 0x00, ARCH_GCN_1_0_1_5 }, 1135 { "v_cmp_f_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_STDMODE, 1136 0x00, ARCH_GCN_1_0_1_5 }, 1080 1137 { "v_cmp_lt_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x01, ARCH_GCN_1_0_1_5 }, 1081 { "v_cmp_lt_f32", GCNENC_VOP3A, GCN_ STDMODE,0x01, ARCH_GCN_1_0_1_5 },1138 { "v_cmp_lt_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x01, ARCH_GCN_1_0_1_5 }, 1082 1139 { "v_cmp_eq_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x02, ARCH_GCN_1_0_1_5 }, 1083 { "v_cmp_eq_f32", GCNENC_VOP3A, GCN_ STDMODE,0x02, ARCH_GCN_1_0_1_5 },1140 { "v_cmp_eq_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x02, ARCH_GCN_1_0_1_5 }, 1084 1141 { "v_cmp_le_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x03, ARCH_GCN_1_0_1_5 }, 1085 { "v_cmp_le_f32", GCNENC_VOP3A, GCN_ STDMODE,0x03, ARCH_GCN_1_0_1_5 },1142 { "v_cmp_le_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x03, ARCH_GCN_1_0_1_5 }, 1086 1143 { "v_cmp_gt_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x04, ARCH_GCN_1_0_1_5 }, 1087 { "v_cmp_gt_f32", GCNENC_VOP3A, GCN_ STDMODE,0x04, ARCH_GCN_1_0_1_5 },1144 { "v_cmp_gt_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x04, ARCH_GCN_1_0_1_5 }, 1088 1145 { "v_cmp_lg_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x05, ARCH_GCN_1_0_1_5 }, 1089 { "v_cmp_lg_f32", GCNENC_VOP3A, GCN_ STDMODE,0x05, ARCH_GCN_1_0_1_5 },1146 { "v_cmp_lg_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x05, ARCH_GCN_1_0_1_5 }, 1090 1147 { "v_cmp_ge_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x06, ARCH_GCN_1_0_1_5 }, 1091 { "v_cmp_ge_f32", GCNENC_VOP3A, GCN_ STDMODE,0x06, ARCH_GCN_1_0_1_5 },1148 { "v_cmp_ge_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x06, ARCH_GCN_1_0_1_5 }, 1092 1149 { "v_cmp_o_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x07, ARCH_GCN_1_0_1_5 }, 1093 { "v_cmp_o_f32", GCNENC_VOP3A, GCN_ STDMODE,0x07, ARCH_GCN_1_0_1_5 },1150 { "v_cmp_o_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x07, ARCH_GCN_1_0_1_5 }, 1094 1151 { "v_cmp_u_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x08, ARCH_GCN_1_0_1_5 }, 1095 { "v_cmp_u_f32", GCNENC_VOP3A, GCN_ STDMODE,0x08, ARCH_GCN_1_0_1_5 },1152 { "v_cmp_u_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x08, ARCH_GCN_1_0_1_5 }, 1096 1153 { "v_cmp_nge_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x09, ARCH_GCN_1_0_1_5 }, 1097 { "v_cmp_nge_f32", GCNENC_VOP3A, GCN_ STDMODE,0x09, ARCH_GCN_1_0_1_5 },1154 { "v_cmp_nge_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x09, ARCH_GCN_1_0_1_5 }, 1098 1155 { "v_cmp_nlg_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x0a, ARCH_GCN_1_0_1_5 }, 1099 { "v_cmp_nlg_f32", GCNENC_VOP3A, GCN_ STDMODE,0x0a, ARCH_GCN_1_0_1_5 },1156 { "v_cmp_nlg_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x0a, ARCH_GCN_1_0_1_5 }, 1100 1157 { "v_cmp_ngt_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x0b, ARCH_GCN_1_0_1_5 }, 1101 { "v_cmp_ngt_f32", GCNENC_VOP3A, GCN_ STDMODE,0x0b, ARCH_GCN_1_0_1_5 },1158 { "v_cmp_ngt_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x0b, ARCH_GCN_1_0_1_5 }, 1102 1159 { "v_cmp_nle_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x0c, ARCH_GCN_1_0_1_5 }, 1103 { "v_cmp_nle_f32", GCNENC_VOP3A, GCN_ STDMODE,0x0c, ARCH_GCN_1_0_1_5 },1160 { "v_cmp_nle_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x0c, ARCH_GCN_1_0_1_5 }, 1104 1161 { "v_cmp_neq_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x0d, ARCH_GCN_1_0_1_5 }, 1105 { "v_cmp_neq_f32", GCNENC_VOP3A, GCN_ STDMODE,0x0d, ARCH_GCN_1_0_1_5 },1162 { "v_cmp_neq_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x0d, ARCH_GCN_1_0_1_5 }, 1106 1163 { "v_cmp_nlt_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x0e, ARCH_GCN_1_0_1_5 }, 1107 { "v_cmp_nlt_f32", GCNENC_VOP3A, GCN_ STDMODE,0x0e, ARCH_GCN_1_0_1_5 },1164 { "v_cmp_nlt_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x0e, ARCH_GCN_1_0_1_5 }, 1108 1165 { "v_cmp_tru_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x0f, ARCH_GCN_1_0_1_5 }, 1109 { "v_cmp_tru_f32", GCNENC_VOP3A, GCN_ STDMODE,0x0f, ARCH_GCN_1_0_1_5 },1166 { "v_cmp_tru_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x0f, ARCH_GCN_1_0_1_5 }, 1110 1167 { "v_cmp_t_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x0f, ARCH_GCN_1_0_1_5 }, 1111 { "v_cmp_t_f32", GCNENC_VOP3A, GCN_ STDMODE,0x0f, ARCH_GCN_1_0_1_5 },1168 { "v_cmp_t_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x0f, ARCH_GCN_1_0_1_5 }, 1112 1169 { "v_cmpx_f_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x10, ARCH_GCN_1_0_1 }, 1113 1170 { "v_cmpx_f_f32", GCNENC_VOP3A, GCN_STDMODE, 0x10, ARCH_GCN_1_0_1 }, … … 1145 1202 { "v_cmpx_t_f32", GCNENC_VOP3A, GCN_STDMODE, 0x1f, ARCH_GCN_1_0_1 }, 1146 1203 { "v_cmpx_f_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x10, ARCH_GCN_1_5 }, 1147 { "v_cmpx_f_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x10, ARCH_GCN_1_5 },1204 { "v_cmpx_f_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x10, ARCH_GCN_1_5 }, 1148 1205 { "v_cmpx_lt_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x11, ARCH_GCN_1_5 }, 1149 { "v_cmpx_lt_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x11, ARCH_GCN_1_5 },1206 { "v_cmpx_lt_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x11, ARCH_GCN_1_5 }, 1150 1207 { "v_cmpx_eq_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x12, ARCH_GCN_1_5 }, 1151 { "v_cmpx_eq_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x12, ARCH_GCN_1_5 },1208 { "v_cmpx_eq_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x12, ARCH_GCN_1_5 }, 1152 1209 { "v_cmpx_le_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x13, ARCH_GCN_1_5 }, 1153 { "v_cmpx_le_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x13, ARCH_GCN_1_5 },1210 { "v_cmpx_le_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x13, ARCH_GCN_1_5 }, 1154 1211 { "v_cmpx_gt_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x14, ARCH_GCN_1_5 }, 1155 { "v_cmpx_gt_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x14, ARCH_GCN_1_5 },1212 { "v_cmpx_gt_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x14, ARCH_GCN_1_5 }, 1156 1213 { "v_cmpx_lg_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x15, ARCH_GCN_1_5 }, 1157 { "v_cmpx_lg_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x15, ARCH_GCN_1_5 },1214 { "v_cmpx_lg_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x15, ARCH_GCN_1_5 }, 1158 1215 { "v_cmpx_ge_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x16, ARCH_GCN_1_5 }, 1159 { "v_cmpx_ge_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x16, ARCH_GCN_1_5 },1216 { "v_cmpx_ge_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x16, ARCH_GCN_1_5 }, 1160 1217 { "v_cmpx_o_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x17, ARCH_GCN_1_5 }, 1161 { "v_cmpx_o_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x17, ARCH_GCN_1_5 },1218 { "v_cmpx_o_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x17, ARCH_GCN_1_5 }, 1162 1219 { "v_cmpx_u_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x18, ARCH_GCN_1_5 }, 1163 { "v_cmpx_u_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x18, ARCH_GCN_1_5 },1220 { "v_cmpx_u_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x18, ARCH_GCN_1_5 }, 1164 1221 { "v_cmpx_nge_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x19, ARCH_GCN_1_5 }, 1165 { "v_cmpx_nge_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x19, ARCH_GCN_1_5 },1222 { "v_cmpx_nge_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x19, ARCH_GCN_1_5 }, 1166 1223 { "v_cmpx_nlg_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x1a, ARCH_GCN_1_5 }, 1167 { "v_cmpx_nlg_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x1a, ARCH_GCN_1_5 },1224 { "v_cmpx_nlg_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x1a, ARCH_GCN_1_5 }, 1168 1225 { "v_cmpx_ngt_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x1b, ARCH_GCN_1_5 }, 1169 { "v_cmpx_ngt_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x1b, ARCH_GCN_1_5 },1226 { "v_cmpx_ngt_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x1b, ARCH_GCN_1_5 }, 1170 1227 { "v_cmpx_nle_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x1c, ARCH_GCN_1_5 }, 1171 { "v_cmpx_nle_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x1c, ARCH_GCN_1_5 },1228 { "v_cmpx_nle_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x1c, ARCH_GCN_1_5 }, 1172 1229 { "v_cmpx_neq_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x1d, ARCH_GCN_1_5 }, 1173 { "v_cmpx_neq_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x1d, ARCH_GCN_1_5 },1230 { "v_cmpx_neq_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x1d, ARCH_GCN_1_5 }, 1174 1231 { "v_cmpx_nlt_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x1e, ARCH_GCN_1_5 }, 1175 { "v_cmpx_nlt_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x1e, ARCH_GCN_1_5 },1232 { "v_cmpx_nlt_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x1e, ARCH_GCN_1_5 }, 1176 1233 { "v_cmpx_tru_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x1f, ARCH_GCN_1_5 }, 1177 { "v_cmpx_tru_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x1f, ARCH_GCN_1_5 },1234 { "v_cmpx_tru_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x1f, ARCH_GCN_1_5 }, 1178 1235 { "v_cmpx_t_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x1f, ARCH_GCN_1_5 }, 1179 { "v_cmpx_t_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x1f, ARCH_GCN_1_5 },1236 { "v_cmpx_t_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x1f, ARCH_GCN_1_5 }, 1180 1237 { "v_cmp_f_f64", GCNENC_VOPC, GCN_REG_ALL_64, 0x20, ARCH_GCN_1_0_1_5 }, 1181 1238 { "v_cmp_f_f64", GCNENC_VOP3A, GCN_REG_ALL_64, 0x20, ARCH_GCN_1_0_1_5 }, … … 1437 1494 { "v_cmp_t_i32", GCNENC_VOP3A, GCN_STDMODE, 0x87, ARCH_GCN_1_0_1_5 }, 1438 1495 { "v_cmp_class_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x88, ARCH_GCN_1_0_1_5 }, 1439 { "v_cmp_class_f32", GCNENC_VOP3A, GCN_ STDMODE,0x88, ARCH_GCN_1_0_1_5 },1496 { "v_cmp_class_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x88, ARCH_GCN_1_0_1_5 }, 1440 1497 { "v_cmp_lt_i16", GCNENC_VOPC, GCN_STDMODE, 0x89, ARCH_GCN_1_5 }, 1441 1498 { "v_cmp_lt_i16", GCNENC_VOP3A, GCN_STDMODE, 0x89, ARCH_GCN_1_5 }, … … 1453 1510 { "v_cmp_ge_i16", GCNENC_VOP3A, GCN_STDMODE, 0x8e, ARCH_GCN_1_5 }, 1454 1511 { "v_cmp_class_f16", GCNENC_VOPC, GCN_F16LIT, 0x8f, ARCH_GCN_1_5 }, 1455 { "v_cmp_class_f16", GCNENC_VOP3A, GCN_ STDMODE,0x8f, ARCH_GCN_1_5 },1512 { "v_cmp_class_f16", GCNENC_VOP3A, GCN_F16LIT, 0x8f, ARCH_GCN_1_5 }, 1456 1513 { "v_cmpx_f_i32", GCNENC_VOPC, GCN_STDMODE, 0x90, ARCH_GCN_1_0_1 }, 1457 1514 { "v_cmpx_f_i32", GCNENC_VOP3A, GCN_STDMODE, 0x90, ARCH_GCN_1_0_1 }, … … 1475 1532 { "v_cmpx_t_i32", GCNENC_VOP3A, GCN_STDMODE, 0x97, ARCH_GCN_1_0_1 }, 1476 1533 { "v_cmpx_class_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x98, ARCH_GCN_1_0_1 }, 1477 { "v_cmpx_class_f32", GCNENC_VOP3A, GCN_ STDMODE,0x98, ARCH_GCN_1_0_1 },1534 { "v_cmpx_class_f32", GCNENC_VOP3A, GCN_FLOATLIT, 0x98, ARCH_GCN_1_0_1 }, 1478 1535 { "v_cmpx_f_i32", GCNENC_VOPC, GCN_VOPC_NOVCC, 0x90, ARCH_GCN_1_5 }, 1479 1536 { "v_cmpx_f_i32", GCNENC_VOP3A, GCN_VOP3_NODST, 0x90, ARCH_GCN_1_5 }, … … 1497 1554 { "v_cmpx_t_i32", GCNENC_VOP3A, GCN_VOP3_NODST, 0x97, ARCH_GCN_1_5 }, 1498 1555 { "v_cmpx_class_f32", GCNENC_VOPC, GCN_FLOATLIT|GCN_VOPC_NOVCC, 0x98, ARCH_GCN_1_5 }, 1499 { "v_cmpx_class_f32", GCNENC_VOP3A, GCN_ VOP3_NODST,0x98, ARCH_GCN_1_5 },1556 { "v_cmpx_class_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_VOP3_NODST, 0x98, ARCH_GCN_1_5 }, 1500 1557 { "v_cmpx_lt_i16", GCNENC_VOPC, GCN_VOPC_NOVCC, 0x99, ARCH_GCN_1_5 }, 1501 1558 { "v_cmpx_lt_i16", GCNENC_VOP3A, GCN_VOP3_NODST, 0x99, ARCH_GCN_1_5 }, … … 1513 1570 { "v_cmpx_ge_i16", GCNENC_VOP3A, GCN_VOP3_NODST, 0x9e, ARCH_GCN_1_5 }, 1514 1571 { "v_cmpx_class_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0x9f, ARCH_GCN_1_5 }, 1515 { "v_cmpx_class_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0x9f, ARCH_GCN_1_5 },1572 { "v_cmpx_class_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0x9f, ARCH_GCN_1_5 }, 1516 1573 { "v_cmp_f_i64", GCNENC_VOPC, GCN_REG_ALL_64, 0xa0, ARCH_GCN_1_0_1_5 }, 1517 1574 { "v_cmp_f_i64", GCNENC_VOP3A, GCN_REG_ALL_64, 0xa0, ARCH_GCN_1_0_1_5 }, … … 1629 1686 { "v_cmp_t_u32", GCNENC_VOP3A, GCN_STDMODE, 0xc7, ARCH_GCN_1_0_1_5 }, 1630 1687 { "v_cmp_f_f16", GCNENC_VOPC, GCN_F16LIT, 0xc8, ARCH_GCN_1_5 }, 1631 { "v_cmp_f_f16", GCNENC_VOP3A, GCN_ STDMODE,0xc8, ARCH_GCN_1_5 },1688 { "v_cmp_f_f16", GCNENC_VOP3A, GCN_F16LIT, 0xc8, ARCH_GCN_1_5 }, 1632 1689 { "v_cmp_lt_f16", GCNENC_VOPC, GCN_F16LIT, 0xc9, ARCH_GCN_1_5 }, 1633 { "v_cmp_lt_f16", GCNENC_VOP3A, GCN_ STDMODE,0xc9, ARCH_GCN_1_5 },1690 { "v_cmp_lt_f16", GCNENC_VOP3A, GCN_F16LIT, 0xc9, ARCH_GCN_1_5 }, 1634 1691 { "v_cmp_eq_f16", GCNENC_VOPC, GCN_F16LIT, 0xca, ARCH_GCN_1_5 }, 1635 { "v_cmp_eq_f16", GCNENC_VOP3A, GCN_ STDMODE,0xca, ARCH_GCN_1_5 },1692 { "v_cmp_eq_f16", GCNENC_VOP3A, GCN_F16LIT, 0xca, ARCH_GCN_1_5 }, 1636 1693 { "v_cmp_le_f16", GCNENC_VOPC, GCN_F16LIT, 0xcb, ARCH_GCN_1_5 }, 1637 { "v_cmp_le_f16", GCNENC_VOP3A, GCN_ STDMODE,0xcb, ARCH_GCN_1_5 },1694 { "v_cmp_le_f16", GCNENC_VOP3A, GCN_F16LIT, 0xcb, ARCH_GCN_1_5 }, 1638 1695 { "v_cmp_gt_f16", GCNENC_VOPC, GCN_F16LIT, 0xcc, ARCH_GCN_1_5 }, 1639 { "v_cmp_gt_f16", GCNENC_VOP3A, GCN_ STDMODE,0xcc, ARCH_GCN_1_5 },1696 { "v_cmp_gt_f16", GCNENC_VOP3A, GCN_F16LIT, 0xcc, ARCH_GCN_1_5 }, 1640 1697 { "v_cmp_lg_f16", GCNENC_VOPC, GCN_F16LIT, 0xcd, ARCH_GCN_1_5 }, 1641 { "v_cmp_lg_f16", GCNENC_VOP3A, GCN_ STDMODE,0xcd, ARCH_GCN_1_5 },1698 { "v_cmp_lg_f16", GCNENC_VOP3A, GCN_F16LIT, 0xcd, ARCH_GCN_1_5 }, 1642 1699 { "v_cmp_ge_f16", GCNENC_VOPC, GCN_F16LIT, 0xce, ARCH_GCN_1_5 }, 1643 { "v_cmp_ge_f16", GCNENC_VOP3A, GCN_ STDMODE,0xce, ARCH_GCN_1_5 },1700 { "v_cmp_ge_f16", GCNENC_VOP3A, GCN_F16LIT, 0xce, ARCH_GCN_1_5 }, 1644 1701 { "v_cmp_o_f16", GCNENC_VOPC, GCN_F16LIT, 0xcf, ARCH_GCN_1_5 }, 1645 { "v_cmp_o_f16", GCNENC_VOP3A, GCN_ STDMODE,0xcf, ARCH_GCN_1_5 },1702 { "v_cmp_o_f16", GCNENC_VOP3A, GCN_F16LIT, 0xcf, ARCH_GCN_1_5 }, 1646 1703 { "v_cmpx_f_u32", GCNENC_VOPC, GCN_STDMODE, 0xd0, ARCH_GCN_1_0_1 }, 1647 1704 { "v_cmpx_f_u32", GCNENC_VOP3A, GCN_STDMODE, 0xd0, ARCH_GCN_1_0_1 }, … … 1685 1742 { "v_cmpx_t_u32", GCNENC_VOP3A, GCN_VOP3_NODST, 0xd7, ARCH_GCN_1_5 }, 1686 1743 { "v_cmpx_f_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xd8, ARCH_GCN_1_5 }, 1687 { "v_cmpx_f_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xd8, ARCH_GCN_1_5 },1744 { "v_cmpx_f_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xd8, ARCH_GCN_1_5 }, 1688 1745 { "v_cmpx_lt_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xd9, ARCH_GCN_1_5 }, 1689 { "v_cmpx_lt_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xd9, ARCH_GCN_1_5 },1746 { "v_cmpx_lt_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xd9, ARCH_GCN_1_5 }, 1690 1747 { "v_cmpx_eq_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xda, ARCH_GCN_1_5 }, 1691 { "v_cmpx_eq_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xda, ARCH_GCN_1_5 },1748 { "v_cmpx_eq_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xda, ARCH_GCN_1_5 }, 1692 1749 { "v_cmpx_le_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xdb, ARCH_GCN_1_5 }, 1693 { "v_cmpx_le_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xdb, ARCH_GCN_1_5 },1750 { "v_cmpx_le_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xdb, ARCH_GCN_1_5 }, 1694 1751 { "v_cmpx_gt_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xdc, ARCH_GCN_1_5 }, 1695 { "v_cmpx_gt_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xdc, ARCH_GCN_1_5 },1752 { "v_cmpx_gt_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xdc, ARCH_GCN_1_5 }, 1696 1753 { "v_cmpx_lg_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xdd, ARCH_GCN_1_5 }, 1697 { "v_cmpx_lg_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xdd, ARCH_GCN_1_5 },1754 { "v_cmpx_lg_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xdd, ARCH_GCN_1_5 }, 1698 1755 { "v_cmpx_ge_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xde, ARCH_GCN_1_5 }, 1699 { "v_cmpx_ge_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xde, ARCH_GCN_1_5 },1756 { "v_cmpx_ge_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xde, ARCH_GCN_1_5 }, 1700 1757 { "v_cmpx_o_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xdf, ARCH_GCN_1_5 }, 1701 { "v_cmpx_o_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xdf, ARCH_GCN_1_5 },1758 { "v_cmpx_o_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xdf, ARCH_GCN_1_5 }, 1702 1759 { "v_cmp_f_u64", GCNENC_VOPC, GCN_REG_ALL_64, 0xe0, ARCH_GCN_1_0_1_5 }, 1703 1760 { "v_cmp_f_u64", GCNENC_VOP3A, GCN_REG_ALL_64, 0xe0, ARCH_GCN_1_0_1_5 }, … … 1721 1778 { "v_cmp_t_u64", GCNENC_VOP3A, GCN_REG_ALL_64, 0xe7, ARCH_GCN_1_0_1_5 }, 1722 1779 { "v_cmp_u_f16", GCNENC_VOPC, GCN_F16LIT, 0xe8, ARCH_GCN_1_5 }, 1723 { "v_cmp_u_f16", GCNENC_VOP3A, GCN_ STDMODE,0xe8, ARCH_GCN_1_5 },1780 { "v_cmp_u_f16", GCNENC_VOP3A, GCN_F16LIT, 0xe8, ARCH_GCN_1_5 }, 1724 1781 { "v_cmp_nge_f16", GCNENC_VOPC, GCN_F16LIT, 0xe9, ARCH_GCN_1_5 }, 1725 { "v_cmp_nge_f16", GCNENC_VOP3A, GCN_ STDMODE,0xe9, ARCH_GCN_1_5 },1782 { "v_cmp_nge_f16", GCNENC_VOP3A, GCN_F16LIT, 0xe9, ARCH_GCN_1_5 }, 1726 1783 { "v_cmp_nlg_f16", GCNENC_VOPC, GCN_F16LIT, 0xea, ARCH_GCN_1_5 }, 1727 { "v_cmp_nlg_f16", GCNENC_VOP3A, GCN_ STDMODE,0xea, ARCH_GCN_1_5 },1784 { "v_cmp_nlg_f16", GCNENC_VOP3A, GCN_F16LIT, 0xea, ARCH_GCN_1_5 }, 1728 1785 { "v_cmp_ngt_f16", GCNENC_VOPC, GCN_F16LIT, 0xeb, ARCH_GCN_1_5 }, 1729 { "v_cmp_ngt_f16", GCNENC_VOP3A, GCN_ STDMODE,0xeb, ARCH_GCN_1_5 },1786 { "v_cmp_ngt_f16", GCNENC_VOP3A, GCN_F16LIT, 0xeb, ARCH_GCN_1_5 }, 1730 1787 { "v_cmp_nle_f16", GCNENC_VOPC, GCN_F16LIT, 0xec, ARCH_GCN_1_5 }, 1731 { "v_cmp_nle_f16", GCNENC_VOP3A, GCN_ STDMODE,0xec, ARCH_GCN_1_5 },1788 { "v_cmp_nle_f16", GCNENC_VOP3A, GCN_F16LIT, 0xec, ARCH_GCN_1_5 }, 1732 1789 { "v_cmp_neq_f16", GCNENC_VOPC, GCN_F16LIT, 0xed, ARCH_GCN_1_5 }, 1733 { "v_cmp_neq_f16", GCNENC_VOP3A, GCN_ STDMODE,0xed, ARCH_GCN_1_5 },1790 { "v_cmp_neq_f16", GCNENC_VOP3A, GCN_F16LIT, 0xed, ARCH_GCN_1_5 }, 1734 1791 { "v_cmp_nlt_f16", GCNENC_VOPC, GCN_F16LIT, 0xee, ARCH_GCN_1_5 }, 1735 { "v_cmp_nlt_f16", GCNENC_VOP3A, GCN_ STDMODE,0xee, ARCH_GCN_1_5 },1792 { "v_cmp_nlt_f16", GCNENC_VOP3A, GCN_F16LIT, 0xee, ARCH_GCN_1_5 }, 1736 1793 { "v_cmp_tru_f16", GCNENC_VOPC, GCN_F16LIT, 0xef, ARCH_GCN_1_5 }, 1737 { "v_cmp_tru_f16", GCNENC_VOP3A, GCN_ STDMODE,0xef, ARCH_GCN_1_5 },1794 { "v_cmp_tru_f16", GCNENC_VOP3A, GCN_F16LIT, 0xef, ARCH_GCN_1_5 }, 1738 1795 { "v_cmp_t_f16", GCNENC_VOPC, GCN_F16LIT, 0xef, ARCH_GCN_1_5 }, 1739 { "v_cmp_t_f16", GCNENC_VOP3A, GCN_ STDMODE,0xef, ARCH_GCN_1_5 },1796 { "v_cmp_t_f16", GCNENC_VOP3A, GCN_F16LIT, 0xef, ARCH_GCN_1_5 }, 1740 1797 { "v_cmpx_f_u64", GCNENC_VOPC, GCN_REG_ALL_64, 0xf0, ARCH_GCN_1_0_1 }, 1741 1798 { "v_cmpx_f_u64", GCNENC_VOP3A, GCN_REG_ALL_64, 0xf0, ARCH_GCN_1_0_1 }, … … 1779 1836 { "v_cmpx_t_u64", GCNENC_VOP3A, GCN_REG_ALL_64|GCN_VOP3_NODST, 0xf7, ARCH_GCN_1_5 }, 1780 1837 { "v_cmpx_u_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xf8, ARCH_GCN_1_5 }, 1781 { "v_cmpx_u_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xf8, ARCH_GCN_1_5 },1838 { "v_cmpx_u_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xf8, ARCH_GCN_1_5 }, 1782 1839 { "v_cmpx_nge_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xf9, ARCH_GCN_1_5 }, 1783 { "v_cmpx_nge_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xf9, ARCH_GCN_1_5 },1840 { "v_cmpx_nge_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xf9, ARCH_GCN_1_5 }, 1784 1841 { "v_cmpx_nlg_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xfa, ARCH_GCN_1_5 }, 1785 { "v_cmpx_nlg_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xfa, ARCH_GCN_1_5 },1842 { "v_cmpx_nlg_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xfa, ARCH_GCN_1_5 }, 1786 1843 { "v_cmpx_ngt_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xfb, ARCH_GCN_1_5 }, 1787 { "v_cmpx_ngt_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xfb, ARCH_GCN_1_5 },1844 { "v_cmpx_ngt_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xfb, ARCH_GCN_1_5 }, 1788 1845 { "v_cmpx_nle_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xfc, ARCH_GCN_1_5 }, 1789 { "v_cmpx_nle_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xfc, ARCH_GCN_1_5 },1846 { "v_cmpx_nle_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xfc, ARCH_GCN_1_5 }, 1790 1847 { "v_cmpx_neq_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xfd, ARCH_GCN_1_5 }, 1791 { "v_cmpx_neq_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xfd, ARCH_GCN_1_5 },1848 { "v_cmpx_neq_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xfd, ARCH_GCN_1_5 }, 1792 1849 { "v_cmpx_nlt_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xfe, ARCH_GCN_1_5 }, 1793 { "v_cmpx_nlt_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xfe, ARCH_GCN_1_5 },1850 { "v_cmpx_nlt_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xfe, ARCH_GCN_1_5 }, 1794 1851 { "v_cmpx_tru_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xff, ARCH_GCN_1_5 }, 1795 { "v_cmpx_tru_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xff, ARCH_GCN_1_5 },1852 { "v_cmpx_tru_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xff, ARCH_GCN_1_5 }, 1796 1853 { "v_cmpx_t_f16", GCNENC_VOPC, GCN_F16LIT|GCN_VOPC_NOVCC, 0xff, ARCH_GCN_1_5 }, 1797 { "v_cmpx_t_f16", GCNENC_VOP3A, GCN_ VOP3_NODST,0xff, ARCH_GCN_1_5 },1854 { "v_cmpx_t_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_VOP3_NODST, 0xff, ARCH_GCN_1_5 }, 1798 1855 { "v_cmp_class_f32", GCNENC_VOPC, GCN_FLOATLIT, 0x10, ARCH_GCN_1_2_4 }, 1799 1856 { "v_cmp_class_f32", GCNENC_VOP3A, GCN_STDMODE, 0x10, ARCH_GCN_1_2_4 }, … … 2256 2313 { "v_mad_i32_i24", GCNENC_VOP3A, GCN_STDMODE, 322, ARCH_GCN_1_0_1_5 }, 2257 2314 { "v_mad_u32_u24", GCNENC_VOP3A, GCN_STDMODE, 323, ARCH_GCN_1_0_1_5 }, 2258 { "v_cubeid_f32", GCNENC_VOP3A, GCN_ STDMODE,324, ARCH_GCN_1_0_1_5 },2259 { "v_cubesc_f32", GCNENC_VOP3A, GCN_ STDMODE,325, ARCH_GCN_1_0_1_5 },2260 { "v_cubetc_f32", GCNENC_VOP3A, GCN_ STDMODE,326, ARCH_GCN_1_0_1_5 },2261 { "v_cubema_f32", GCNENC_VOP3A, GCN_ STDMODE,327, ARCH_GCN_1_0_1_5 },2315 { "v_cubeid_f32", GCNENC_VOP3A, GCN_FLOATLIT, 324, ARCH_GCN_1_0_1_5 }, 2316 { "v_cubesc_f32", GCNENC_VOP3A, GCN_FLOATLIT, 325, ARCH_GCN_1_0_1_5 }, 2317 { "v_cubetc_f32", GCNENC_VOP3A, GCN_FLOATLIT, 326, ARCH_GCN_1_0_1_5 }, 2318 { "v_cubema_f32", GCNENC_VOP3A, GCN_FLOATLIT, 327, ARCH_GCN_1_0_1_5 }, 2262 2319 { "v_bfe_u32", GCNENC_VOP3A, GCN_STDMODE, 328, ARCH_GCN_1_0_1_5 }, 2263 2320 { "v_bfe_i32", GCNENC_VOP3A, GCN_STDMODE, 329, ARCH_GCN_1_0_1_5 }, … … 2269 2326 { "v_alignbyte_b32", GCNENC_VOP3A, GCN_STDMODE, 335, ARCH_GCN_1_0_1_5 }, 2270 2327 { "v_mullit_f32", GCNENC_VOP3A, GCN_STDMODE, 336, ARCH_GCN_1_0_1_5 }, 2271 { "v_min3_f32", GCNENC_VOP3A, GCN_ STDMODE,337, ARCH_GCN_1_0_1_5 },2328 { "v_min3_f32", GCNENC_VOP3A, GCN_FLOATLIT, 337, ARCH_GCN_1_0_1_5 }, 2272 2329 { "v_min3_i32", GCNENC_VOP3A, GCN_STDMODE, 338, ARCH_GCN_1_0_1_5 }, 2273 2330 { "v_min3_u32", GCNENC_VOP3A, GCN_STDMODE, 339, ARCH_GCN_1_0_1_5 }, 2274 { "v_max3_f32", GCNENC_VOP3A, GCN_ STDMODE,340, ARCH_GCN_1_0_1_5 },2331 { "v_max3_f32", GCNENC_VOP3A, GCN_FLOATLIT, 340, ARCH_GCN_1_0_1_5 }, 2275 2332 { "v_max3_i32", GCNENC_VOP3A, GCN_STDMODE, 341, ARCH_GCN_1_0_1_5 }, 2276 2333 { "v_max3_u32", GCNENC_VOP3A, GCN_STDMODE, 342, ARCH_GCN_1_0_1_5 }, 2277 { "v_med3_f32", GCNENC_VOP3A, GCN_ STDMODE,343, ARCH_GCN_1_0_1_5 },2334 { "v_med3_f32", GCNENC_VOP3A, GCN_FLOATLIT, 343, ARCH_GCN_1_0_1_5 }, 2278 2335 { "v_med3_i32", GCNENC_VOP3A, GCN_STDMODE, 344, ARCH_GCN_1_0_1_5 }, 2279 2336 { "v_med3_u32", GCNENC_VOP3A, GCN_STDMODE, 345, ARCH_GCN_1_0_1_5 }, … … 2282 2339 { "v_sad_u16", GCNENC_VOP3A, GCN_STDMODE, 348, ARCH_GCN_1_0_1_5 }, 2283 2340 { "v_sad_u32", GCNENC_VOP3A, GCN_STDMODE, 349, ARCH_GCN_1_0_1_5 }, 2284 { "v_cvt_pk_u8_f32", GCNENC_VOP3A, GCN_ STDMODE,350, ARCH_GCN_1_0_1_5 },2285 { "v_div_fixup_f32", GCNENC_VOP3A, GCN_ STDMODE,351, ARCH_GCN_1_0_1_5 },2341 { "v_cvt_pk_u8_f32", GCNENC_VOP3A, GCN_FLOATLIT, 350, ARCH_GCN_1_0_1_5 }, 2342 { "v_div_fixup_f32", GCNENC_VOP3A, GCN_FLOATLIT, 351, ARCH_GCN_1_0_1_5 }, 2286 2343 { "v_div_fixup_f64", GCNENC_VOP3A, GCN_REG_ALL_64, 352, ARCH_GCN_1_0_1_5 }, 2287 2344 { "v_lshl_b64", GCNENC_VOP3A, GCN_REG_DS0_64|GCN_SRC2_NONE,353, ARCH_GCN_1_0_1 }, … … 2315 2372 { "v_mad_i64_i32", GCNENC_VOP3B, GCN_REG_DS2_64|GCN_DST_VCC_VSRC2, 2316 2373 375, ARCH_GCN_1_1_5 }, 2317 { "v_div_scale_f32", GCNENC_VOP3B, GCN_ STDMODE|GCN_S0EQS12|GCN_VCC_IMPL_WRITE,2374 { "v_div_scale_f32", GCNENC_VOP3B, GCN_FLOATLIT|GCN_S0EQS12|GCN_VCC_IMPL_WRITE, 2318 2375 365, ARCH_GCN_1_0_1_5 }, 2319 2376 { "v_div_scale_f64", GCNENC_VOP3B, GCN_REG_ALL_64|GCN_S0EQS12|GCN_VCC_IMPL_WRITE, … … 2500 2557 { "v_sub_co_u32", GCNENC_VOP3B, GCN_DST_VCC|GCN_SRC2_NONE, 784, ARCH_GCN_1_5 }, 2501 2558 { "v_pack_b32_f16", GCNENC_VOP3A, GCN_SRC2_NONE, 785, ARCH_GCN_1_5 }, 2502 { "v_cvt_pknorm_i16_f16", GCNENC_VOP3A, GCN_ SRC2_NONE,786, ARCH_GCN_1_5 },2503 { "v_cvt_pknorm_u16_f16", GCNENC_VOP3A, GCN_ SRC2_NONE,787, ARCH_GCN_1_5 },2559 { "v_cvt_pknorm_i16_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_SRC2_NONE, 786, ARCH_GCN_1_5 }, 2560 { "v_cvt_pknorm_u16_f16", GCNENC_VOP3A, GCN_F16LIT|GCN_SRC2_NONE, 787, ARCH_GCN_1_5 }, 2504 2561 { "v_lshlrev_b16", GCNENC_VOP3A, GCN_SRC2_NONE, 788, ARCH_GCN_1_5 }, 2505 2562 { "v_subrev_co_u32", GCNENC_VOP3B, GCN_DST_VCC|GCN_SRC2_NONE, 793, ARCH_GCN_1_5 }, … … 2512 2569 { "v_lshl_add_u32", GCNENC_VOP3A, GCN_STDMODE, 838, ARCH_GCN_1_5 }, 2513 2570 { "v_add_lshl_u32", GCNENC_VOP3A, GCN_STDMODE, 839, ARCH_GCN_1_5 }, 2514 { "v_fma_f16", GCNENC_VOP3A, GCN_ STDMODE,843, ARCH_GCN_1_5 },2515 { "v_min3_f16", GCNENC_VOP3A, GCN_ STDMODE,849, ARCH_GCN_1_5 },2571 { "v_fma_f16", GCNENC_VOP3A, GCN_F16LIT, 843, ARCH_GCN_1_5 }, 2572 { "v_min3_f16", GCNENC_VOP3A, GCN_F16LIT, 849, ARCH_GCN_1_5 }, 2516 2573 { "v_min3_i16", GCNENC_VOP3A, GCN_STDMODE, 850, ARCH_GCN_1_5 }, 2517 2574 { "v_min3_u16", GCNENC_VOP3A, GCN_STDMODE, 851, ARCH_GCN_1_5 }, 2518 { "v_max3_f16", GCNENC_VOP3A, GCN_ STDMODE,852, ARCH_GCN_1_5 },2575 { "v_max3_f16", GCNENC_VOP3A, GCN_F16LIT, 852, ARCH_GCN_1_5 }, 2519 2576 { "v_max3_i16", GCNENC_VOP3A, GCN_STDMODE, 853, ARCH_GCN_1_5 }, 2520 2577 { "v_max3_u16", GCNENC_VOP3A, GCN_STDMODE, 854, ARCH_GCN_1_5 }, 2521 { "v_med3_f16", GCNENC_VOP3A, GCN_ STDMODE,855, ARCH_GCN_1_5 },2578 { "v_med3_f16", GCNENC_VOP3A, GCN_F16LIT, 855, ARCH_GCN_1_5 }, 2522 2579 { "v_med3_i16", GCNENC_VOP3A, GCN_STDMODE, 856, ARCH_GCN_1_5 }, 2523 2580 { "v_med3_u16", GCNENC_VOP3A, GCN_STDMODE, 857, ARCH_GCN_1_5 }, … … 2525 2582 858, ARCH_GCN_1_5 }, 2526 2583 { "v_mad_i16", GCNENC_VOP3A, GCN_STDMODE, 862, ARCH_GCN_1_5 }, 2527 { "v_div_fixup_f16", GCNENC_VOP3A, GCN_ STDMODE,863, ARCH_GCN_1_5 },2584 { "v_div_fixup_f16", GCNENC_VOP3A, GCN_F16LIT, 863, ARCH_GCN_1_5 }, 2528 2585 { "v_readlane_b32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01|GCN_VOP3_DS1_SGPR|GCN_VOP_NOWVSZ, 2529 2586 864, ARCH_GCN_1_5 }, 2530 2587 { "v_writelane_b32", GCNENC_VOP3A, GCN_VOP3_VOP2_DS01|GCN_VOP3_SRC1_SGPR|GCN_VOP_NOWVSZ, 2531 2588 865, ARCH_GCN_1_5 }, 2532 { "v_ldexp_f32", GCNENC_VOP3A, GCN_ SRC2_NONE,866, ARCH_GCN_1_5 },2589 { "v_ldexp_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_SRC2_NONE, 866, ARCH_GCN_1_5 }, 2533 2590 { "v_bfm_b32", GCNENC_VOP3A, GCN_SRC2_NONE, 867, ARCH_GCN_1_5 }, 2534 2591 { "v_bcnt_u32_b32", GCNENC_VOP3A, GCN_SRC2_NONE, 868, ARCH_GCN_1_5 }, 2535 2592 { "v_mbcnt_lo_u32_b32", GCNENC_VOP3A, GCN_SRC2_NONE, 869, ARCH_GCN_1_5 }, 2536 2593 { "v_mbcnt_hi_u32_b32", GCNENC_VOP3A, GCN_SRC2_NONE, 870, ARCH_GCN_1_5 }, 2537 { "v_cvt_pknorm_i16_f32", GCNENC_VOP3A, GCN_ SRC2_NONE,872, ARCH_GCN_1_5 },2538 { "v_cvt_pknorm_u16_f32", GCNENC_VOP3A, GCN_ SRC2_NONE,873, ARCH_GCN_1_5 },2594 { "v_cvt_pknorm_i16_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_SRC2_NONE, 872, ARCH_GCN_1_5 }, 2595 { "v_cvt_pknorm_u16_f32", GCNENC_VOP3A, GCN_FLOATLIT|GCN_SRC2_NONE, 873, ARCH_GCN_1_5 }, 2539 2596 { "v_cvt_pk_u16_u32", GCNENC_VOP3A, GCN_SRC2_NONE, 874, ARCH_GCN_1_5 }, 2540 2597 { "v_cvt_pk_i16_i32", GCNENC_VOP3A, GCN_SRC2_NONE, 875, ARCH_GCN_1_5 }, … … 2563 2620 { "v_pk_max_u16", GCNENC_VOP3P, GCN_SRC2_NONE, 12, ARCH_GCN_1_5 }, 2564 2621 { "v_pk_min_u16", GCNENC_VOP3P, GCN_SRC2_NONE, 13, ARCH_GCN_1_5 }, 2565 { "v_pk_fma_f16", GCNENC_VOP3P, GCN_ STDMODE,14, ARCH_GCN_1_5 },2566 { "v_pk_add_f16", GCNENC_VOP3P, GCN_ SRC2_NONE,15, ARCH_GCN_1_5 },2567 { "v_pk_mul_f16", GCNENC_VOP3P, GCN_ SRC2_NONE,16, ARCH_GCN_1_5 },2568 { "v_pk_min_f16", GCNENC_VOP3P, GCN_ SRC2_NONE,17, ARCH_GCN_1_5 },2569 { "v_pk_max_f16", GCNENC_VOP3P, GCN_ SRC2_NONE,18, ARCH_GCN_1_5 },2570 { "v_dot2_f32_f16", GCNENC_VOP3P, GCN_ STDMODE,19, ARCH_NAVI_DL },2622 { "v_pk_fma_f16", GCNENC_VOP3P, GCN_F16LIT, 14, ARCH_GCN_1_5 }, 2623 { "v_pk_add_f16", GCNENC_VOP3P, GCN_F16LIT|GCN_SRC2_NONE, 15, ARCH_GCN_1_5 }, 2624 { "v_pk_mul_f16", GCNENC_VOP3P, GCN_F16LIT|GCN_SRC2_NONE, 16, ARCH_GCN_1_5 }, 2625 { "v_pk_min_f16", GCNENC_VOP3P, GCN_F16LIT|GCN_SRC2_NONE, 17, ARCH_GCN_1_5 }, 2626 { "v_pk_max_f16", GCNENC_VOP3P, GCN_F16LIT|GCN_SRC2_NONE, 18, ARCH_GCN_1_5 }, 2627 { "v_dot2_f32_f16", GCNENC_VOP3P, GCN_F16LIT, 19, ARCH_NAVI_DL }, 2571 2628 { "v_dot2_i32_i16", GCNENC_VOP3P, GCN_STDMODE, 20, ARCH_NAVI_DL }, 2572 2629 { "v_dot2_u32_u16", GCNENC_VOP3P, GCN_STDMODE, 21, ARCH_NAVI_DL }, … … 2575 2632 { "v_dot8_i32_i4", GCNENC_VOP3P, GCN_STDMODE, 24, ARCH_NAVI_DL }, 2576 2633 { "v_dot8_u32_u4", GCNENC_VOP3P, GCN_STDMODE, 25, ARCH_NAVI_DL }, 2577 { "v_fma_mix_f32", GCNENC_VOP3P, GCN_ STDMODE,32, ARCH_GCN_1_5 },2578 { "v_fma_mixlo_f16", GCNENC_VOP3P, GCN_ STDMODE,33, ARCH_GCN_1_5 },2579 { "v_fma_mixhi_f16", GCNENC_VOP3P, GCN_ STDMODE,34, ARCH_GCN_1_5 },2634 { "v_fma_mix_f32", GCNENC_VOP3P, GCN_FLOATLIT, 32, ARCH_GCN_1_5 }, 2635 { "v_fma_mixlo_f16", GCNENC_VOP3P, GCN_F16LIT, 33, ARCH_GCN_1_5 }, 2636 { "v_fma_mixhi_f16", GCNENC_VOP3P, GCN_F16LIT, 34, ARCH_GCN_1_5 }, 2580 2637 { "v_interp_p1_f32", GCNENC_VINTRP, GCN_STDMODE, 0, ARCH_GCN_ALL }, 2581 2638 { "v_interp_p2_f32", GCNENC_VINTRP, GCN_STDMODE, 1, ARCH_GCN_ALL }, -
CLRadeonExtender/trunk/amdasm/GCNInternals.h
r4774 r4831 151 151 // others 152 152 GCN_SBASE4 = 0x10, /// SBASE requires 4 registers 153 GCN_FLOATLIT = 0x100, /// float literal 154 GCN_F16LIT = 0x200, /// half literal 153 GCN_FLOATLIT = 0x40000000U, /// float literal 154 GCN_F16LIT = 0x80000000U, /// half literal 155 GCN_LITMASK = 0xc0000000U, 155 156 GCN_SMRD_ONLYDST = 0x30, // only destination (no other operands) 156 157 GCN_SMEM_SDATA_IMM = 0x40, // treat SDATA as immediate -
CLRadeonExtender/trunk/tests/amdasm/GCNAsmOpc11.cpp
r4816 r4831 944 944 { " v_cvt_f32_f16 v158, -23.56h", 0x7f3c16ffU, 0xcde4U, true, true, "" }, 945 945 /* constant immediates */ 946 { " v_cvt_f 32_f16 v158, 0.0", 0x7f3c1680U, 0, false, true, "" },947 { " v_cvt_f 32_f16 v158, 0.5s", 0x7f3c16f0U, 0, false, true, "" },948 { " v_cvt_f 32_f16 v158, -0.5s", 0x7f3c16f1U, 0, false, true, "" },949 { " v_cvt_f 32_f16 v158, 1.s", 0x7f3c16f2U, 0, false, true, "" },950 { " v_cvt_f 32_f16 v158, -1.s", 0x7f3c16f3U, 0, false, true, "" },951 { " v_cvt_f 32_f16 v158, 2.s", 0x7f3c16f4U, 0, false, true, "" },952 { " v_cvt_f 32_f16 v158, -2.s", 0x7f3c16f5U, 0, false, true, "" },953 { " v_cvt_f 32_f16 v158, 4.s", 0x7f3c16f6U, 0, false, true, "" },954 { " v_cvt_f 32_f16 v158, -4.s", 0x7f3c16f7U, 0, false, true, "" },946 { " v_cvt_f16_f32 v158, 0.0", 0x7f3c1480U, 0, false, true, "" }, 947 { " v_cvt_f16_f32 v158, 0.5s", 0x7f3c14f0U, 0, false, true, "" }, 948 { " v_cvt_f16_f32 v158, -0.5s", 0x7f3c14f1U, 0, false, true, "" }, 949 { " v_cvt_f16_f32 v158, 1.s", 0x7f3c14f2U, 0, false, true, "" }, 950 { " v_cvt_f16_f32 v158, -1.s", 0x7f3c14f3U, 0, false, true, "" }, 951 { " v_cvt_f16_f32 v158, 2.s", 0x7f3c14f4U, 0, false, true, "" }, 952 { " v_cvt_f16_f32 v158, -2.s", 0x7f3c14f5U, 0, false, true, "" }, 953 { " v_cvt_f16_f32 v158, 4.s", 0x7f3c14f6U, 0, false, true, "" }, 954 { " v_cvt_f16_f32 v158, -4.s", 0x7f3c14f7U, 0, false, true, "" }, 955 955 { " v_cvt_f32_f64 v158, 0.5l", 0x7f3c1ef0U, 0, false, true, "" }, 956 956 { " v_cvt_f32_f64 v158, -0.5l", 0x7f3c1ef1U, 0, false, true, "" }, -
CLRadeonExtender/trunk/tests/amdasm/GCNAsmOpc15.cpp
r4830 r4831 1366 1366 { " v_cvt_f32_f16 v158, -23.56h", 0x7f3c16ffU, 0xcde4U, true, true, "" }, 1367 1367 /* constant immediates */ 1368 { " v_cvt_f 32_f16 v158, 0.0", 0x7f3c1680U, 0, false, true, "" },1369 { " v_cvt_f 32_f16 v158, 0.5s", 0x7f3c16f0U, 0, false, true, "" },1370 { " v_cvt_f 32_f16 v158, -0.5s", 0x7f3c16f1U, 0, false, true, "" },1371 { " v_cvt_f 32_f16 v158, 1.s", 0x7f3c16f2U, 0, false, true, "" },1372 { " v_cvt_f 32_f16 v158, -1.s", 0x7f3c16f3U, 0, false, true, "" },1373 { " v_cvt_f 32_f16 v158, 2.s", 0x7f3c16f4U, 0, false, true, "" },1374 { " v_cvt_f 32_f16 v158, -2.s", 0x7f3c16f5U, 0, false, true, "" },1375 { " v_cvt_f 32_f16 v158, 4.s", 0x7f3c16f6U, 0, false, true, "" },1376 { " v_cvt_f 32_f16 v158, -4.s", 0x7f3c16f7U, 0, false, true, "" },1368 { " v_cvt_f16_f32 v158, 0.0", 0x7f3c1480U, 0, false, true, "" }, 1369 { " v_cvt_f16_f32 v158, 0.5s", 0x7f3c14f0U, 0, false, true, "" }, 1370 { " v_cvt_f16_f32 v158, -0.5s", 0x7f3c14f1U, 0, false, true, "" }, 1371 { " v_cvt_f16_f32 v158, 1.s", 0x7f3c14f2U, 0, false, true, "" }, 1372 { " v_cvt_f16_f32 v158, -1.s", 0x7f3c14f3U, 0, false, true, "" }, 1373 { " v_cvt_f16_f32 v158, 2.s", 0x7f3c14f4U, 0, false, true, "" }, 1374 { " v_cvt_f16_f32 v158, -2.s", 0x7f3c14f5U, 0, false, true, "" }, 1375 { " v_cvt_f16_f32 v158, 4.s", 0x7f3c14f6U, 0, false, true, "" }, 1376 { " v_cvt_f16_f32 v158, -4.s", 0x7f3c14f7U, 0, false, true, "" }, 1377 1377 { " v_cvt_f32_f64 v158, 0.5l", 0x7f3c1ef0U, 0, false, true, "" }, 1378 1378 { " v_cvt_f32_f64 v158, -0.5l", 0x7f3c1ef1U, 0, false, true, "" }, -
CLRadeonExtender/trunk/tests/amdasm/GCNDisasmOpc11.cpp
r4748 r4831 463 463 "0x40000000 /* 2f */\n" }, 464 464 { 0x7f3c174fU, 0, false, " v_cvt_f32_f16 v158, v79\n" }, 465 { 0x7f3c16ffU, 0x3d4cU, true, " v_cvt_f32_f16 v158, 0x3d4c \n" },465 { 0x7f3c16ffU, 0x3d4cU, true, " v_cvt_f32_f16 v158, 0x3d4c /* 1.3242h */\n" }, 466 466 { 0x7f3c194fU, 0, false, " v_cvt_rpi_i32_f32 v158, v79\n" }, 467 467 { 0x7f3c18ffU, 0x40000000U, true, " v_cvt_rpi_i32_f32 v158, " -
CLRadeonExtender/trunk/tests/amdasm/GCNDisasmOpc12.cpp
r3575 r4831 693 693 "0x40000000 /* 2f */\n" }, 694 694 { 0x7f3c174fU, 0, false, " v_cvt_f32_f16 v158, v79\n" }, 695 { 0x7f3c16ffU, 0x3d4cU, true, " v_cvt_f32_f16 v158, 0x3d4c \n" },695 { 0x7f3c16ffU, 0x3d4cU, true, " v_cvt_f32_f16 v158, 0x3d4c /* 1.3242h */\n" }, 696 696 { 0x7f3c194fU, 0, false, " v_cvt_rpi_i32_f32 v158, v79\n" }, 697 697 { 0x7f3c18ffU, 0x40000000U, true, " v_cvt_rpi_i32_f32 v158, " -
CLRadeonExtender/trunk/tests/amdasm/GCNDisasmOpc15.cpp
r4798 r4831 709 709 "0x40000000 /* 2f */\n" }, 710 710 { 0x7f3c174fU, 0, false, " v_cvt_f32_f16 v158, v79\n" }, 711 { 0x7f3c16ffU, 0x3d4cU, true, " v_cvt_f32_f16 v158, 0x3d4c \n" },711 { 0x7f3c16ffU, 0x3d4cU, true, " v_cvt_f32_f16 v158, 0x3d4c /* 1.3242h */\n" }, 712 712 { 0x7f3c194fU, 0, false, " v_cvt_rpi_i32_f32 v158, v79\n" }, 713 713 { 0x7f3c18ffU, 0x40000000U, true, " v_cvt_rpi_i32_f32 v158, "
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