Changeset 4992 in CLRX


Ignore:
Timestamp:
Sep 23, 2019, 4:15:19 PM (3 weeks ago)
Author:
matszpk
Message:

CLRadeonExtender: CLRXDocs: Update docs - add description for new pseudo-ops.

Location:
CLRadeonExtender/trunk/doc
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • CLRadeonExtender/trunk/doc/ClrxAsmPseudoOps.md

    r4875 r4992  
    9494This pseudo-operation should to be at begin of source.
    9595Choose AMD Catalyst new (introduced for OpenCL 2.0 support) program binary format.
     96
     97### .amd3
     98
     99This pseudo-operation should to be at begin of source.
     100Choose ROCm LLV10 binary format with metadata V3 format -
     101new AMD OpenCL format for Navi (GCN1.5).
    96102
    97103### .arch
  • CLRadeonExtender/trunk/doc/ClrxAsmRocm.md

    r4880 r4992  
    7070### .arg
    7171
    72 Syntax arg: .arg [NAME]\[, "TYPENAME"], SIZE, [ALIGN], VALUEKIND, VALUETYPE[,POINTEEALIGN]\[, ADDRSPACE]\[,ACCQUAL]\[,ACTACCQUAL] \[FLAG1\] \[FLAG2\]...
    73 
    74 This pseudo-op must be inside kernel configuration (`.config`).
    75 Define kernel argument in metadata info. The argument name, type name, alignment are
     72Syntax: .arg [NAME]\[, "TYPENAME"], SIZE, [ALIGN], VALUEKIND, VALUETYPE[,POINTEEALIGN]\[, ADDRSPACE]\[,ACCQUAL]\[,ACTACCQUAL] \[FLAG1\] \[FLAG2\]...
     73
     74or for LLVM10 binary format:
     75
     76Syntax: .arg [NAME]\[, "TYPENAME"], SIZE, [OFFSET], VALUEKIND, VALUETYPE[,POINTEEALIGN]\[, ADDRSPACE]\[,ACCQUAL]\[,ACTACCQUAL] \[FLAG1\] \[FLAG2\]...
     77
     78This pseudo-op must be inside kernel configuration (`.config`).
     79Define kernel argument in metadata info. The argument name, type name, alignment, offset are
    7680optional. The ADDRSPACE is address space and it present only if value kind is
    7781`globalbuf` or `dynshptr`. The POINTEEALIGN is pointee alignment in bytes and it present
     
    286290`group_segment_align` field in kernel configuration.
    287291
     292### .group_segment_fixes_size
     293
     294Syntax: .group_segment_fixes_size SIZE
     295
     296This pseudo-op must be inside kernel configuration (`.config`). Set
     297`workgroup_group_segment_byte_size` in kernel configuration.
     298
    288299### .ieeemode
    289300
     
    355366`kernel_code_prefetch_byte_size` field in kernel configuration.
    356367
     368### .llvm10binfmt
     369
     370Enable LLVM10 binary format (from AMD OpenCL for GCN1.5 Navi).
     371
    357372### .localsize
    358373
     
    455470
    456471This pseudo-operation must be inside kernel. Go to metadata (metadata ELF note) section.
     472
     473### .metadatav3
     474
     475Enable metadata V3 format.
    457476
    458477### .newbinfmt
     
    481500will be ignored. SCRATCH_EN bit will be ignored.
    482501
     502### .pgmrsrc3
     503
     504Syntax: .pgmrsrc3 VALUE
     505
     506This pseudo-op must be inside kernel configuration (`.config`).
     507Define value of the PGMRSRC3 (only for GCN1.5 Navi).
     508
    483509### .printf
    484510
     
    510536`private_segment_alignment` field in kernel configuration. Value must be a power of two.
    511537
     538### .private_segment_fixed_size
     539
     540Syntax: .private_segment_fixed_size SIZE
     541
     542This pseudo-op must be inside kernel configuration (`.config`). Set
     543`workitem_private_segment_byte_size` field in kernel configuration.
     544
    512545### .privmode
    513546
     
    559592It counts SGPR registers including VCC, FLAT_SCRATCH and XNACK_MASK.
    560593
     594### .shared_vgprs
     595
     596Syntax: .shared_vgprs REGNUM
     597
     598
     599This pseudo-op must be inside kernel configuration (`.config`). Set number of shared vector
     600registers between two 32-lane waves (only for GCN1.5 Navi).
     601
    561602### .spilledsgprs
    562603
     
    659700This pseudo-op must be inside kernel configuration (`.config`). Enable
    660701`is_xnack_enabled` field in kernel configuration.
     702
     703### .use_wave32
     704
     705This pseudo-op must be inside kernel configuration (`.config`). Enable
     70632-lane wave (only for GCN1.5 Navi).
    661707
    662708### .userdatanum
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